PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
Rev. 6 — 1 March 2013
Product data sheet
1. General description
The PCA9512A/B is a hot swappable I
2
C-bus and SMBus buffer that allows I/O card
insertion into a live backplane without corruption of the data and clock buses and includes
two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems
while maintaining the best noise margin for each voltage level. Either pin may be powered
with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply
voltage is higher. Control circuitry prevents the backplane from being connected to the
card until a stop bit or bus idle occurs on the backplane without bus contention on the
card. When the connection is made, the PCA9512A/B provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated
13 Dec 2010), so the PCA9512B will be discontinued in the near future and is not
recommended for new designs.
The PCA9512A/B rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9512A/B incorporates a digital
input pin that enables and disables the rise time accelerators on all four SDAn and SCLn
pins.
During insertion, the PCA9512A/B SDAn and SCLn pins are precharged to 1 V to
minimize the current required to charge the parasitic capacitance of the chip.
The incremental offset design of the PCA9510A/11A/12A/12B/13A/14A I/O drivers allows
them to be connected to another PCA9510A/11A/12A/12B/13A/14A device in series or in
parallel and to the I
2
C compliant side of static offset bus buffers, but not to the static offset
side of those bus buffers.
2. Features and benefits
Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and
SCL corruption during live board insertion and removal from multipoint backplane
systems
Compatible with I
2
C-bus Standard mode, I
2
C-bus Fast mode, and SMBus standards
Built-in
V/t
rise time accelerators on all SDA and SCL lines (0.6 V threshold) with
ability to disable
V/t
rise time accelerator through the ACC pin for lightly loaded
systems, requires the bus pull-up voltage and respective supply voltage (V
CC
or V
CC2
)
to be the same
5 V to 3.3 V level translation with optimum noise margin
High-impedance SDAn and SCLn pins for V
CC
or V
CC2
= 0 V
1 V precharge on all SDAn and SCLn pins
Supports clock stretching and multiple master arbitration and synchronization
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
Operating power supply voltage range: 2.7 V to 5.5 V
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO8, TSSOP8 (MSOP8)
3. Applications
cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are
required to be inserted or removed from an operating system
4. Feature selection
Table 1.
Feature
Idle detect
High-impedance SDAn, SCLn pins for V
CC
= 0 V
Feature selection chart
PCA9510A PCA9511A PCA9512A/B PCA9513A PCA9514A
yes
yes
yes
yes
yes
-
-
yes
-
yes
-
yes
yes
yes
yes
-
-
yes
yes
-
yes
yes
yes
-
yes
yes
-
-
yes
yes
yes
yes
-
yes
yes
-
-
-
Rise time accelerator circuitry on SDAn and SCLn pins -
Rise time accelerator circuitry hardware disable pin for -
lightly loaded systems
Rise time accelerator threshold 0.8 V versus 0.6 V
improves noise margin
Ready open-drain output
Two V
CC
pins to support 5 V to 3.3 V level translation
with improved noise margins
1 V precharge on all SDAn and SCLn pins
-
yes
-
in only
92
A
current source on SCLIN and SDAIN for PICMG -
applications
PCA9512A_PCA9512B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 1 March 2013
2 of 27
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
5. Ordering information
Table 2.
Ordering information
Topside
mark
PA9512A
PA9512B
9512A
9512B
TSSOP8
[1]
plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
Package
Name
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Type number
PCA9512AD
PCA9512BD
PCA9512ADP
PCA9512BDP
[1]
Also known as MSOP8.
5.1 Ordering options
Table 3.
Ordering options
Orderable
part number
PCA9512AD,112
PCA9512AD,118
PCA9512BD
PCA9512ADP
PCA9512BDP
PCA9512BD,118
PCA9512ADP,118
PCA9512BDP,118
Package
Packing method
Minimum
order
quantity
2000
2500
2500
2500
2500
Temperature range
Type number
PCA9512AD
SO8
SO8
SO8
TSSOP8
TSSOP8
standard marking *
IC’s tube - DSC bulk pack
reel 13” Q1/T1
*standard mark SMD
reel 13” Q1/T1
*standard mark SMD
reel 13” Q1/T1
*standard mark SMD
reel 13” Q1/T1
*standard mark SMD
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
PCA9512A_PCA9512B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 1 March 2013
3 of 27
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
6. Block diagram
PCA9512A/B
V
CC
2 mA
2 mA
V
CC2
ACC
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
CONNECT
100 kΩ
RCH1
SLEW RATE
DETECTOR
SDAOUT
CONNECT
100 kΩ
RCH3
SDAIN
CONNECT
1 VOLT
PRECHARGE
100 kΩ
RCH2
2 mA
100 kΩ
RCH4
2 mA
ACC
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
SLEW RATE
DETECTOR
ACC
SCLIN
SCLOUT
CONNECT
CONNECT
LEVEL
SHIFTER
STOP BIT AND
BUS IDLE
0.55V
CC
/
0.45V
CC
20 pF
0.5 μA
0.55V
CC
/
0.45V
CC
UVLO
100 μs
DELAY
CONNECT
UVLO
CONNECT
RD
S
QB
GND
0.5 pF
002aag555
Fig 1.
Block diagram of PCA9512A/B
PCA9512A_PCA9512B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 1 March 2013
4 of 27
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
7. Pinning information
7.1 Pinning
V
CC2
SCLOUT
SCLIN
GND
1
2
3
4
002aab789
8
V
CC
SDAOUT
SDAIN
ACC
V
CC2
SCLOUT
SCLIN
GND
1
2
3
4
002aab790
8
V
CC
SDAOUT
SDAIN
ACC
PCA9512AD
PCA9512BD
7
6
5
PCA9512ADP
PCA9512BDP
7
6
5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
7.2 Pin description
Table 4.
Symbol
V
CC2
SCLOUT
SCLIN
GND
ACC
Pin description
Pin
1
2
3
4
5
Description
Supply voltage for devices on the card I
2
C-bus. Connect pull-up resistors
from SDAOUT and SCLOUT to this pin.
serial clock output to and from the SCL bus on the card
serial clock input to and from the SCL bus on the backplane
ground supply; connect this pin to a ground plane for best results.
CMOS threshold digital input pin that enables and disables the rise time
accelerators on all four SDAn and SCLn pins. ACC enables all accelerators
when set to V
CC2
, and turns them off when set to GND.
serial data input to and from the SDA bus on the backplane
serial data output to and from the SDA bus on the card
supply voltage; from the backplane, connect pull-up resistors from SDAIN
and SCLIN to this pin.
SDAIN
SDAOUT
V
CC
6
7
8
8. Functional description
Refer to
Figure 1 “Block diagram of PCA9512A/B”.
Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated
13 Dec 2010), so the PCA9512B will be discontinued in the near future and is not
recommended for new designs. Customers should continue using the PCA9512A or move
to the PCA9512A during the next refresh if they are currently using the PCA9512B.
Description of the PCA9512A operation applies equally to the PCA9512B for the
remainder of this data sheet.
8.1 Start-up
When the PCA9512A is powered up, either V
CC
or V
CC2
may rise first, within a short time
of each other and either may be more positive or they may be equal, however the
PCA9512A will not leave the undervoltage lockout or initialization state until both V
CC
and
V
CC2
have gone above 2.5 V. If either V
CC
or V
CC2
drops below 2.0 V it will return to the
undervoltage lockout state.
PCA9512A_PCA9512B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 1 March 2013
5 of 27
