INTEGRATED CIRCUITS
PCA9512
Level shifting hot swappable
I
2
C and SMBus buffer
Product data sheet
2004 Oct 05
Philips
Semiconductors
Philips Semiconductors
Product data sheet
Level shifting hot swappable I
2
C and SMBus buffer
PCA9512
DESCRIPTION
The PCA9512 is a hot swappable I
2
C and SMBus buffer that allows
I/O card insertion into a live backplane without corruption of the data
and clock buses and includes two dedicated supply voltage pins to
provide level shifting between 3.3 V and 5 V systems while
maintaining the best noise margin for each voltage level. Either pin
may be powered with supply voltages ranging from 2.7 V to 5.5 V
with no constraints on which supply voltage is higher. Control
circuitry prevents the backplane from being connected to the card
until a stop bit or bus idle occurs on the backplane without bus
contention on the card. When the connection is made, the PCA9512
provides bi-directional buffering, keeping the backplane and card
capacitances isolated.
The dynamic offset design of the PCA9510/11/12/13/14 I/O drivers
allow them to be connected to another PCA9510/11/12/13/14 device
in series or in parallel and to the A side of the PCA9517. The
PCA9510/11/12/13/14 can
not
connect to the static offset I/Os used
on the PCA9515/15A/16/16A/17 B side and PCA9518.
PIN CONFIGURATION
TOP VIEW
V
CC2
1
SCLOUT
SCLIN
GND
2
3
4
8
7
6
5
V
CC
SDAOUT
SDAIN
ACC
FEATURES
•
Bi-directional buffer for SDA and SCL lines increases fanout and
•
Compatible with I
2
C standard mode, I
2
C fast mode, and SMBus
standards
to disable
∆V/∆t
rise time accelerators through the ACC pin for
lightly loaded systems
prevents SDA and SCL corruption during live board insertion and
removal from multi-point backplane systems
Figure 1. Pin configuration.
SW02070
PIN DESCRIPTION
PIN
1
SYMBOL
V
CC2
DESCRIPTION
Supply voltage for devices on the card
I
2
C-buses. Connect pull-up resistors from
SDAOUT and SCLOUT to this pin.
Serial clock output to and from the SCL bus
on the card.
Serial clock input to and from the SCL bus
on the backplane.
Ground. Connect this pin to a ground plane
for best results.
CMOS threshold digital input pin that
enables and disables the rise-time
accelerators on all four SDA and SCL pins.
ACC enables all accelerators when set to
V
CC2
, and turns them off when set to GND.
Serial data input to and from the SDA bus on
the backplane/long distance bus.
Serial data output to and from the SDA bus
on the card.
Power supply. From the backplane, connect
pull-up resistors from SDAIN and SCLIN to
this pin.
•
∆V/∆t
rise time accelerators on all SDA and SCL lines with ability
•
5 V to 3.3 V level translation with optimum noise margin
•
High-impedance SDA, SCL pins for V
CC
or V
CC2
= 0 V
•
1 V precharge on all SDA and SCL lines
•
Supports clock stretching and multiple master
arbitration/synchronization
2
3
4
5
SCLOUT
SCLIN
GND
ACC
•
Operating power supply voltage range: 2.7 V to 5.5 V
•
5.5 V tolerant I/Os
•
0 kHz to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latch-up testing is done to JESDEC Standard JESD78 which
•
Packages offered: SO8, TSSOP8 (MSOP8)
APPLICATION
exceeds 100 mA
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
6
7
8
SDAIN
SDAOUT
V
CC
•
cPCI, VME, AdvancedTCA cards and other multi-point backplane
cards that are required to be inserted or removed from an
operating system.
ORDERING INFORMATION
PACKAGES
8-pin plastic SO
8-pin plastic TSSOP (MSOP)
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
ORDER CODE
PCA9512D
PCA9512DP
TOPSIDE MARK
PCA9512
9512
DRAWING NUMBER
SOT96-1
SOT505-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
2004 Oct 05
2
Philips Semiconductors
Product data sheet
Level shifting hot swappable I
2
C and SMBus buffer
PCA9512
TYPICAL APPLICATION
V
CC
5V
R1
10 kΩ
R2
10 kΩ
C2
0.01
µF
C1
0.01
µF
R3
10 kΩ
R4
10 kΩ
R5
10 kΩ
CARD_V
CC
3 V
V
CC
SDA
SDAIN
V
CC2
SDAOUT
CARD_SDA
SCL
SCLIN
SCLOUT
CARD_SCL
C5*
0.01
µF
C3*
0.01
µF
C4*
0.01
µF
PCA9512
GND
ACC
C6*
0.01
µF
* CAPACITORS NOT REQUIRED IF BUS IS SUFFICIENTLY LOADED
SW02068
Figure 2. Typical application
BLOCK DIAGRAM
V
CC
8
2 mA
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
CONNECT
100 kΩ
RCH1
1 VOLT
PRECHARGE
100 kΩ
RCH2
2 mA
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
CONNECT
CONNECT
2 mA
SLEW RATE
DETECTOR
2
100 kΩ
RCH4
CONNECT
CONNECT
100 kΩ
RCH3
2 mA
SLEW RATE
DETECTOR
7
1
V
CC2
A
CC
SDAIN 6
SDAOUT
A
CC
5
ACC
SCLIN 3
SCLOUT
0.5
µA
0.55V
CC
/
0.45V
CC
95
µs
DELAY
STOP BIT AND
BUS IDLE
0.55V
CC
/
0.45V
CC
20 pF
UVLO
RD
QB
S
CONNECT
CONNECT
UVLO
4
0.5 pF
GND
SW02069
Figure 3. Block diagram.
2004 Oct 05
3
Philips Semiconductors
Product data sheet
Level shifting hot swappable I
2
C and SMBus buffer
PCA9512
FEATURE SELECTION CHART
FEATURES
Idle detect
High impedance SDA, SCL pins for V
CC
= 0 V
Rise time accelerator circuitry on all SDA and SCL lines
Rise time accelerator circuitry hardware disable pin for lightly loaded
systems
Rise time accelerator threshold 0.8 V vs 0.6 V improves noise margin
Ready open drain output
Two V
CC
pins to support 5 V to 3.3 V level translation with improved noise
margins
1 V precharge on all SDA and SCL lines
92
µA
current source on SCLIN and SDAIN for PICMG applications
PCA9510
Yes
Yes
—
—
—
Yes
—
IN only
—
PCA9511
Yes
Yes
Yes
—
—
Yes
—
Yes
—
PCA9512
Yes
Yes
Yes
Yes
—
—
Yes
Yes
—
PCA9513
Yes
Yes
Yes
—
Yes
Yes
—
—
Yes
PCA9514
Yes
Yes
Yes
—
Yes
Yes
—
—
—
OPERATION
Start-up
When the PCA9512 is powered up either V
CC
or V
CC2
may rise first
and either may be more positive or they may can be equal, however
the PCA9512 will not leave the under voltage lock out/initialization
state until both V
CC
and V
CC2
have gone above 2.5 V. If either V
CC
or V
CC2
drops below 2.0 V it will return to the under voltage lock
out/initialization state. In the under voltage lock out state the
connection circuitry is disabled, the rise time accelerators are
disabled, and the precharge circuitry is also disabled. After both V
CC
and V
CC2
are valid, independent of which is higher, the PCA9512
enters the initialization state, during this state the 1 V precharge
circuitry is activated and pulls up the SDA and SCL pins to 1 V
through individual 100 kΩ nominal resistors. At the end of the
initialization state the “Stop Bit And Bus Idle” detect circuit is
enabled. When all the SDA and SCL pins have been HIGH for the
bus idle time or when all pins are HIGH and a stop condition is seen
on the SDAIN and SCLIN pins, the connect circuitry is activated,
connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1 V
precharge circuitry is disabled when the connection is made, unless
the ACC pin is LOW, the rise time accelerators are enabled at this
time also.
Connection Circuitry
Once the connection circuitry is activated, the behavior of SDAIN
and SDAOUT as well as SCLIN and SCLOUT become identical with
each acting as a bidirectional buffer that isolated the input bus
capacitance from the output bus capacitance while communicating
the logic levels. If V
CC
≠
V
CC2
, then a level shifting function is also
performed between input and output. A LOW forced on either
SDAIN or SDAOUT will cause the other pin to be driven LOW by the
PCA9512. The same is also true for the SCL pins. Noise between
0.7V
CC
and V
CC
on the SDAIN and SCLIN pins and 0.7V
CC2
and
V
CC2
on the SDAOUT and SCLOUT pins is generally ignored
because a falling edge is only recognized when it falls below the
0.7V
CC
for SDAIN and SCLIN (or 0.7V
CC2
for SDAOUT and
SCLOUT pins) with a slew rate of at least 1.25 V/µs. When a falling
edge is seen on one pin the other pin in the pair turns on a pull down
driver that is reference to a small voltage above the falling pin. The
driver will pull the pin down at a slow rate determined by the driver
and the load. The first falling pin may have a fast or slow slew rate, if
it is faster than the pull down slew rate then the initial pull down rate
will continue until it is LOW. If the first falling pin has a slow slew rate
then the second pin will be pulled down at its initial slew rate only
until it is just above the first pin voltage then they will both continue
down at the slew rate of the first. Once both sides are LOW they will
remain LOW until all the external drivers have stopped driving
LOWs. If both sides are being driven LOW to the same or nearly the
same value by external drivers, which is the case for clock
stretching and is typically the case for acknowledge, and one side
external driver stops driving, that pin will rise and rise above the
nominal offset voltage until the internal driver catches up and pulls it
back down to the offset voltage. This bounce is worst for low
capacitances and low resistances, and may become excessive.
When the last external driver stops driving a LOW, that pin will
bounce up and settle out just above the other pin as both rise
together with a slew rate determined by the internal slew rate control
and the RC time constant. As long as the slew rate is at least 1.25
V/µs, when the pin voltage exceed 0.6 V the rise time accelerator
circuits are turned on and the pull down driver is turned off. If the
ACC pin is LOW the rise time accelerator circuits will be disabled
but the pull down driver will still turn off.
2004 Oct 05
4
Philips Semiconductors
Product data sheet
Level shifting hot swappable I
2
C and SMBus buffer
PCA9512
Maximum number of devices in series
Each buffer adds about 0.065 V dynamic level offset at 25
°C
with
the offset larger at higher temperatures. Maximum offset (V
OS
) is
0.150 V. The LOW level at the signal origination end (master) is
dependent upon the load and the only specification point is the
I
2
C-bus specification of 3 mA will produce V
OL
< 0.4 V, although if
lightly loaded the V
OL
may be
∼0.1
V. Assuming V
OL
= 0.1 V and
V
OS
= 0.1 V, the level after four buffers would be 0.5 V, which is only
about 0.1 V below the threshold of the rising edge accelerator (about
0.6 V). With great care a system with four buffers may work, but as
the V
OL
moves up from 0.1 V, noise or bounces on the line will result
in firing the rising edge accelerator thus introducing false clock
edges. Generally it is recommended to limit the number of buffers in
series to two.
The PCA9510 (rise time accelerator is permanently disabled) and
the PCA9512 (rise time accelerator can be turned off) are a little
different with the rise time accelerator turned off because the rise
time accelerator will not pull the node up, but the same logic that
turns on the accelerator turns the pull-down off. If the V
IL
is above
∼0.6
V and a rising edge is detected, the pull-down will turn off and
will not turn back on until a falling edge is detected; so if the noise is
small enough it may be possible to use more than two PCA9510 or
PCA9512 parts in series but is not recommended.
is the only part driving the node. The common node will rise to 0.5 V
before Buffer B’s output turns on, if the pull-up is strong the node will
bounce. If the bounce goes above the threshold for the rising edge
accelerator
∼0.6
V the accelerators on both Buffer A and Buffer C
will fire contending with the output of Buffer B. The node on the input
of Buffer A will go HIGH as will the input node of Buffer C. After the
common node voltage is stable for a while the rising edge
accelerators will turn off and the common node will return to
∼0.5
V
because the Buffer B is still on. The voltage at both the Master and
Slave C nodes would then fall to
∼0.6
V until Slave B turned off. This
would not cause a failure on the data line as long as the return to
0.5 V on the common node (∼0.6 V at the Master and Slave C)
occurred before the data setup time. If this were the SCL line, the
parts on Buffer A and Buffer C would see a false clock rather than a
stretched clock, which would cause a system error.
Propagation Delays
The delay for a rising edge is determined by the combined pull-up
current from the bus resistors and the PCA9512 and the effective
capacitance on the lines. If the pull-up currents are the same, any
difference in capacitance between the two sides. The t
PLH
may be
negative if the output capacitance is less than the input capacitance
and would be positive if the output capacitance is larger than the
input capacitance, when the currents are the same.
The t
PHL
can never be negative because the output does not start to
fall until the input is below 0.7V
CC
(or 0.7V
CC2
for SDAOUT and
SCLOUT) and the output pull down turn on has a nonzero delay,
and the output has a limited maximum slew rate and even it the
input slew rate is slow enough that the output catches up it will still
lag the falling voltage of the input by the offset voltage, The
maximum t
PHL
occurs when the input is driven LOW with zero delay
and the output is still limited by its turn on delay and the falling edge
slew rate, The output falling edge slew rate (which is a function of
temperature, V
CC
or V
CC2
, and process) as well as load current and
load capacitance.
buffer A
MASTER
common
node
buffer B
SLAVE B
buffer C
SLAVE C
SW02353
Figure 4.
Consider a system with three buffers connected to a common node
and communication between the Master and Slave B that are
connected at either end of Buffer A and Buffer B in series as shown
in Figure 4. Consider if the V
OL
at the input of Buffer A is 0.3 V and
the V
OL
of Slave B (when acknowledging) is 0.4 V with the direction
changing from Master to Slave B and then from Slave B to Master.
Before the direction change you would observe V
IL
at the input of
Buffer A of 0.3 V and its output, the common node, is
∼0.4
V. The
output of Buffer B and Buffer C would be
∼0.5
V, but Slave B is
driving 0.4 V, so the voltage at Slave B is 0.4 V. The output of
Buffer C is
∼0.5
V. When the Master pull-down turns off, the input of
Buffer A rises and so does its output, the common node, because it
Rise Time Accelerators
During positive bus transitions a 2 mA current source is switched on
to quickly slew the SDA and SCL lines HIGH once the input level of
0.6 V is exceeded. The rising edge rate should be at least 1.25 V/µs
to guarantee turn on of the accelerators.
ACC Boost Current Enable
Users having lightly loaded systems may wish to disable the
rise-time accelerators. Driving this pin to ground turns off the
rise-time accelerators on all four SDA and SCL pins. Driving this pin
to the V
CC2
voltage enables normal operation of the rise-time
accelerators.
2004 Oct 05
5
