PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
Rev. 07 — 13 November 2006
Product data sheet
1. General description
The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General
Purpose parallel Input/Output (GPIO) expansion for I
2
C-bus/SMBus applications and
were developed to enhance the NXP Semiconductors family of I
2
C-bus I/O expanders.
The improvements include higher drive capability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O
expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push buttons, LEDs, fans, etc.
The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output
selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity
Inversion register (active HIGH or active LOW operation). The system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input Port or Output Port register. The
polarity of the read register can be inverted with the Polarity Inversion register. All
registers can be read by the system master. Although pin-to-pin and I
2
C-bus address
compatible with the PCF8574 series, software changes are required due to the
enhancements and are discussed in
Application Note AN469.
The PCA9554/PCA9554A open-drain interrupt output is activated when any input state
differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus. The PCA9554A is identical to the PCA9554
except that the fixed I
2
C-bus address is different allowing up to sixteen of these devices
(eight of each) on the same I
2
C-bus/SMBus.
2. Features
I
I
I
I
I
I
I
I
I
I
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
8 I/O pins which default to 8 inputs
0 Hz to 400 kHz clock frequency
NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: DIP16, SO16, SSOP16, SSOP20, TSSOP16,
HVQFN16 (2 versions: 4
×
4
×
0.85 mm and 3
×
3
×
0.85 mm), and bare die
3. Ordering information
Table 1.
Ordering information
T
amb
=
−
40
°
C to +85
°
C.
Type number
PCA9554N
PCA9554AN
PCA9554D
PCA9554AD
PCA9554DB
PCA9554ADB
PCA9554TS
PCA9554ATS
PCA9554PW
PCA9554APW
PCA9554BS
PCA9554ABS
PCA9554BS3
PCA9554ABS3
PCA9554U
Topside mark
PCA9554N
PCA9554AN
PCA9554D
PCA9554AD
9554DB
9554A
PCA9554
PA9554A
9554DH
9554ADH
9554
554A
P54
54A
-
bare die
HVQFN16
HVQFN16
TSSOP16
SSOP20
SSOP16
SO16
Package
Name
DIP16
Description
plastic dual in-line package; 16 leads (300 mil);
long body
plastic small outline package; 16 leads;
body width 7.5 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic shrink small outline package; 20 leads;
body width 4.4 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4
×
4
×
0.85 mm
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3
×
3
×
0.85 mm
-
Version
SOT38-1
SOT162-1
SOT338-1
SOT266-1
SOT403-1
SOT629-1
SOT758-1
-
PCA9554_9554A_7
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 — 13 November 2006
2 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
4. Block diagram
PCA9554/PCA9554A
A0
A1
A2
8-bit
SCL
SDA
INPUT
FILTER
I
2
C-BUS/SMBus
CONTROL
write pulse
V
DD
POWER-ON
RESET
read pulse
INPUT/
OUTPUT
PORTS
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V
DD
V
SS
LP
FILTER
002aac492
INT
All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9554/PCA9554A
PCA9554_9554A_7
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 — 13 November 2006
3 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
5. Pinning information
5.1 Pinning
PCA9554N
PCA9554AN
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
1
2
3
4
5
6
7
8
002aac485
16 V
DD
15 SDA
14 SCL
A0
13 INT
12 IO7
11 IO6
10 IO5
9
IO4
A1
A2
IO0
IO1
IO2
IO3
V
SS
1
2
3
4
5
6
7
8
002aac486
16 V
DD
15 SDA
14 SCL
13 INT
12 IO7
11 IO6
10 IO5
9
IO4
PCA9554D
PCA9554AD
Fig 2. Pin configuration for DIP16
Fig 3. Pin configuration for SO16
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
1
2
3
4
5
6
7
8
002aac487
16 V
DD
15 SDA
14 SCL
13 INT
12 IO7
11 IO6
10 IO5
9
IO4
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
1
2
3
4
5
6
7
8
002aac488
16 V
DD
15 SDA
14 SCL
13 INT
12 IO7
11 IO6
10 IO5
9
IO4
PCA9554DB
PCA9554ADB
PCA9554PW
PCA9554APW
Fig 4. Pin configuration for SSOP16
Fig 5. Pin configuration for TSSOP16
PCA9554_9554A_7
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 — 13 November 2006
4 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
INT
SCL
n.c.
SDA
V
DD
A0
A1
n.c.
A2
1
2
3
4
5
6
7
8
9
20 IO7
19 IO6
18 n.c.
17 IO5
16 IO4
15 V
SS
14 IO3
13 n.c.
12 IO2
11 IO1
002aac489
PCA9554TS
PCA9554ATS
IO0 10
Fig 6. Pin configuration for SSOP20
PCA9554BS
PCA9554ABS
13 SDA
14 V
DD
16 A1
15 A0
terminal 1
index area
terminal 1
index area
PCA9554BS3
PCA9554ABS3
13 SDA
12 SCL
11 INT
10 IO7
9
5
6
7
8
IO6
IO5
14 V
DD
IO4
16 A1
1
2
3
4
IO3
15 A0
V
SS
A2
IO0
IO1
IO2
1
2
3
4
5
6
7
8
12 SCL
11 INT
10 IO7
9
IO6
A2
IO0
IO1
IO2
V
SS
IO3
IO4
IO5
002aac490
002aac491
Transparent top view
Transparent top view
Fig 7. Pin configuration for HVQFN16
(SOT629-1)
Fig 8. Pin configuration for HVQFN16
(SOT758-1)
PCA9554_9554A_7
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 — 13 November 2006
5 of 30
