INTEGRATED CIRCUITS
PCA9556
Octal SMBus and I
2
C registered interface
Product data
Supersedes data of 2000 Nov 13
2002 Mar 28
Philips
Semiconductors
Philips Semiconductors
Product data
Octal SMBus and I
2
C registered interface
PCA9556
The power-on reset puts the registers in their default state and
initializes the SMBus state machine. The RESET pin causes the
same reset/initialization to occur without depowering the part.
The PCA9557 8-bit I
2
C SMBus I/O port with reset is the higher
performance pin-for-pin replacement for the PCA9556.
PIN CONFIGURATION
SCL 1
SDA
2
16 V
DD
15 RESET
14 I/O7
13 I/O6
12 I/O5
11 I/O4
10 I/O3
9
I/O2
FEATURES
•
SMBus compliance with fixed 3.3V voltage levels
•
Operating power supply voltage range of 3.0 V – 5.5 V
•
Active high polarity inverter register
•
Each I/O is configurable as an input or output
•
Active low reset pin
•
Low leakage current on power-down
•
Noise filter on SCL/SDA inputs
•
No glitch on power-up
•
Internal power-on reset
•
8 I/O pins which default to 8 inputs
•
High impedance open drain on I/O0
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
A0 3
A1 4
A2 5
I/O0 6
I/O1 7
V
SS
8
su01045
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
1
2
3
4
5
6
7
8
9–14
15
16
SYMBOL
SCL
SDA
A0
A1
A2
I/O0
I/O1
V
SS
I/O2–I/O7
RESET
V
DD
FUNCTION
Serial clock line
Serial data line
Address input 0
Address input 1
Address input 2
I/O0 (open drain)
I/O1
Supply GROUND
I/O2 to I/O7
External reset (active LOW)
Supply voltage
•
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
DESCRIPTION
The PCA9556 is a silicon CMOS circuit which provides parallel
input/output expansion for SMBus applications. The PCA9556
consists of an 8-bit input port register, 8-bit output port register, and
an SMBus interface. It has low current consumption and a high
impedance open drain output pin, I/O0.
The SMBus system master can reset the PCA9556 in the event of a
timeout by asserting a LOW on the reset input. The SMBus system
master can also invert the PCA9556 inputs by writing to the active
HIGH polarity inversion bits. Finally, the system master can enable
the PCA9556’s I/Os as either inputs or outputs by writing to the
configuration register.
ORDERING INFORMATION
PACKAGES
16-Pin Plastic TSSOP
TEMPERATURE RANGE
–40 to +85
°C
ORDER CODE
PCA9556PW
DRAWING NUMBER
SOT403-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I
2
C patent.
I
2
C is a trademark of Philips Semiconductors Corporation.
2002 Mar 28
2
853-2138 27929
Philips Semiconductors
Product data
Octal SMBus and I
2
C registered interface
PCA9556
BLOCK DIAGRAM
A0
A1
A2
SCL
SDA
INPUT
FILTER
8-BIT
INPUT/
OUTPUT
PORTS
I/O0
I/O1
I/O2
SMBus
CONTROL
I/O3
I/O4
I/O5
I/O6
I/O7
WRITE pulse
READ pulse
V
DD
V
SS
POWER-ON
RESET
RESET
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
SW00793
Figure 2. Block diagram
SYSTEM DIAGRAM
Input Port
Q7
Polarity Inversion
Q7
Configuration
Q7
Output Port
1.1 KΩ
Q7
I/O0
6
V
CC
= 16
GND = 8
Q6
1.1 KΩ
15
RESET
Q5
Q6
Q6
Q6
I/O1
7
Q5
Q5
Q5
I/O2
9
1.6 KΩ
1
SCL
I
2
C/SMBus
Interface
logic
Q4
Q4
Q4
Q4
I/O3
10
1.6 KΩ
2
SDA
Q3
Q3
Q3
Q3
I/O4
11
5
A2
or
1.1 KΩ
Q2
Q2
Q2
Q2
I/O5
12
4
A1
or
1.1 KΩ
Q1
Q1
Q1
Q1
I/O6
13
3
A0
or
1.1 KΩ
Q0
Q0
Q0
Q0
I/O7
14
SW00794
Figure 3. System diagram
2002 Mar 28
3
Philips Semiconductors
Product data
Octal SMBus and I
2
C registered interface
PCA9556
REGISTERS
Command Byte
Command
0
1
2
3
Protocol
Read byte
Read/write byte
Read/write byte
Read/write byte
Function
Input port register
Output port register
Polarity inversion register
Configuration register
Register 2 — Polarity Inversion Register
bit
default
N7
1
N6
1
N5
1
N4
1
N3
0
N2
0
N1
0
N0
0
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
This register enables polarity inversion of pins defined as inputs by
register 3. If a bit in this register is set (written with ‘1’), the
corresponding port pin’s polarity is inverted. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s original
polarity is retained.
Register 3 — Configuration Register
bit
default
Register 0 — Input Port Register
I7
I6
I5
I4
I3
I2
I1
I0
This register is an read-only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by register 3. Writes to this register have no effect.
C7
1
C6
1
C5
1
C4
1
C3
1
C2
1
C1
1
C0
1
This register configures the directions of the I/O pins. If a bit in this
register is set, the corresponding port pin is enabled as an input with
high impedance output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output.
Register 1 — Output Port Register
bit
default
O7
0
O6
0
O5
0
O4
0
O3
0
O2
0
O1
0
O0
0
RESET
Power-on Reset
When power is applied to V
DD
, an internal power-on reset holds the
PCA9556 in a reset state until V
DD
has reached V
POR
. At that point,
the reset condition is released and the PCA9556 registers and
SMBus state machine will initialize to their default states.
This register reflects the outgoing logic levels of the pins defined as
outputs by register 3. Bit values in this register have no effect on
pins defined as inputs. In turn, reads from this register reflect the
value that is in the flip-flop controlling the output selection, NOT the
actual pin value.
External Reset
A reset can be accomplished by holding the RESET pin low for a
minimum of T
W
. The PCA9556 registers and SMBus/I
2
C state
machine will be held in their default state until the RESET input is
once again high. This input typically requires a pull-up to 3.3 V V
CC.
2002 Mar 28
4
Philips Semiconductors
Product data
Octal SMBus and I
2
C registered interface
PCA9556
SIMPLIFIED SCHEMATIC OF I/O0
DATA FROM
SHIFT REGISTER
CONFIGURATION
REGISTER
DATA FROM
SHIFT REGISTER
WRITE
CONFIGURATION
PULSE
WRITE PULSE
D
FF
C
K
Q
D
FF
I/O0
C
K
Q
ESD PROTECTION DIODE
Q
Q
OUTPUT PORT
REGISTER DATA
OUTPUT
PORT
REGISTER
INPUT PORT
REGISTER
D
FF
READ PULSE
C
K
Q
Q
V
SS
INPUT PORT
REGISTER DATA
DATA FROM
SHIFT REGISTER
WRITE POLARITY
PULSE
D
FF
C
K
Q
POLARITY
REGISTER DATA
Q
POLARITY
INVERSION
REGISTER
SW00795
NOTE:
On power–up or reset, all registers return to default values.
Figure 4. Simplified schematic of I/O0
2002 Mar 28
5
