32 Bit PCI Master/Target
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32 Bit PCI Master/Target
Overview
Peripheral Component Interconnect (PCI)
is a widely accepted bus standard
that is used in many applications including telecommunications, embedded
systems, high performance peripheral cards, and networking.
Lattice's PCI IP core
provides an ideal solution that meets the needs of today's
high performance PCI applications. It is fully compliant with the PCI Local Bus
Specification, revision 2.2 for speeds up to 66MHz. The PCI core provides a
customizable 32/64-bit master/target
or
target solution. The core bridges the gap between the PCI interface and a specific design application, providing an
integrated PCI solution. The PCI solution allows designers to focus on the application rather than on the PCI specification,
resulting in a faster time-to-market.
The Lattice PCI offering is available in a number of configurations covering 32-bit
PCI, 64-bit PCI, 32-bit local bus, 64-bit local bus, master/target and target
applications. In this document, details of 64-bit operation and master operation
only apply when relevant. The appendix to the user's guide shows what cores are
available on which devices.
Features
Available as 32/64-Bit PCI Bus and 32/64-Bit Local Bus
PCI SIG Local Bus Specification, Revision 3.0 Compliant
64-Bit Addressing Support (Dual Address Cycle)
Fast Back-to-Back Transaction Support
Supports Zero Wait State Transactions
Special Cycle Transaction Support
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32 Bit PCI Master/Target
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Capabilities List Pointer Support
Parity Error Detection
Up to Six Base Address Registers (BARs)
Customizable Configuration Space
Up to 66MHz PCI
Fully Synchronous Design
Performance and Resource Utilization
LatticeECP3
Bus Width
32-bit
32-bit
IPexpress Mode
Master/Target 33 MHz
Master/Target 66 MHz
Slices
683
1076
LUTs
1059
1691
1
Registers
640
661
sysMEM EBRs
-
-
External
Pins
50
50
f
MAX
(MHz)
33
66
1. Performance and utilization data are generated using an LFE3-95EA-7FN1156CES device with Lattice Diamond 1.0 software.
Performance may vary when using a different software version or targeting a different device density or speed grade within the
LatticeECP3 family.
LatticeECP2M
Bus Width
32-bit
32-bit
IPexpress Mode
Master/Target 33 MHz
Master/Target 66 MHz
Slices
856
1086
LUTs
1068
1700
1
Registers
642
663
sysMEM EBRs
-
-
External
Pins
50
50
f
MAX
(MHz)
33
66
1. Performance and utilization data are generated using an LFE2M-35E-6F672C device with Lattice Diamond 1.0 software. Performance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family.
LatticeECP2
1
Bus Width
32-bit
32-bit
IPexpress Mode
Master/Target 33 MHz
Master/Target 66 MHz
Slices
856
1086
LUTs
1068
1700
Registers
642
663
sysMEM EBRs
-
-
External
Pins
50
50
f
MAX
(MHz)
33
66
1. Performance and utilization data are generated using an LFE2-20E-6F672C device with Lattice Diamond 1.0 software. Performance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 family.
LatticeEC/P
Bus Width
32-bit
32-bit
IPexpress Mode
Master/Target 33 MHz
Master/Target 66 MHz
Slices
846
1083
LUTs
1060
1690
1
Registers
642
663
sysMEM EBRs
-
-
External
Pins
50
50
f
MAX
(MHz)
33
66
1. Performance and utilization data are generated using an LFEC33E-5F672C device with Lattice Diamond 1.0 software. Performance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP/EC
family.
LatticeSC
Bus Width
32-bit
32-bit
IPexpress Mode
Master/Target 33 MHz
Master/Target 66 MHz
Slices
724
1085
LUTs
1050
1722
1
Registers
640
663
sysMEM EBRs
-
-
External
Pins
50
50
f
MAX
(MHz)
33
66
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32 Bit PCI Master/Target
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Performance may vary when using a different software version or targeting a different device density or speed grade within the
LatticeSC family.
MachXO2
Bus Width
32-bit
IPexpress Mode
Master/Target 33 MHz
Slices
406
LUTs
803
1
Registers
582
sysMEM EBRs
-
External
Pins
50
f
MAX
(MHz)
33
1. Preliminary information. Performance and utilization data are generated using an LCMXO2-1200HC-6TG144CES device with Lattice
Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed
grade within the MachXO2 family.
MachXO
Bus Width
32-bit
IPexpress Mode
Master/Target 33 MHz
Slices
542
LUTs
1060
1
Registers
642
sysMEM EBRs
-
External
Pins
50
f
MAX
(MHz)
33
1. Performance and utilization data are generated using an LCMXO2280C-5FT324C device with Lattice Diamond 1.0 software.
Performance may vary when using a different software version or targeting a different device density or speed grade within the
MachXO family.
LatticeXP2
1
Bus Width
32-bit
32-bit
IPexpress Mode
Master/Target 33 MHz
Master/Target 66 MHz
Slices
851
1081
LUTs
1060
1692
Registers
640
661
sysMEM EBRs
-
-
External
Pins
50
50
f
MAX
(MHz)
33
66
1. Performance and utilization data are generated using an LFXP2-17E-6F484C device with Lattice Diamond 1.0 software. Performance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.
LatticeXP
Bus Width
32-bit
32-bit
IPexpress Mode
Master/Target 33 MHz
Master/Target 66 MHz
Slices
846
1083
LUTs
1060
1690
1
Registers
642
663
sysMEM EBRs
-
-
External
Pins
50
50
f
MAX
(MHz)
33
66
1. Performance and utilization data are generated using an LFXP20C-5F484C device with Lattice Diamond 1.0 software. Performance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP family
Ordering Information
Family
LatticeECP3
LatticeECP2M
LatticeECP2
LatticeECP/EC
LatticeSC
MachXO2
MachXO
LatticeXP2
LatticeXP
Bus Width
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
Bus Speed
33MHz, 66MHz
33MHz, 66MHz
33MHz, 66MHz
33MHz, 66MHz
33MHz, 66MHz
33MHz
33MHz
33MHz, 66MHz
33MHz, 66MHz
Master/Target
Part Number
PCI-MT32-E3-U6
PCI-MT32-PM-U6
PCI-MT32-P2-U6
PCI-MT32-E2-U6
PCI-MT32-SC-U6
PCI-MT32-M2-U1
PCI-MT32-XO-U6
PCI-MT32-X2-U6
PCI-MT32-XM-U6
IP Version:
PCI Master/Target 33MHz = 6.6, PCI Master/Target 66MHz = 6.4
Evaluate:
To download a full evaluation version of this IP, go to the Lattice IP Server tab in the IPexpress Main Window.
All ispLeverCORE IP cores and modules available for download are visible on this tab. *PCI cores for ORCA and
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32 Bit PCI Master/Target
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ispXPGA,devices are supported by the Lattice factory-configurable design flow.
Purchase:
To find out how to purchase the IP Core, please contact your
local Lattice Sales Office.
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10/17/2011
