MAN-00640B-000
Rev. 1.4
October 10, 1994
PCI0640B
PCI to IDE Chip
CMD Technology, Inc.
1 Vanderbilt
Irvine, California 92718
(714) 454-0800
This page left blank intentionally.
2
Table of Contents
1
Interface Specifications
1.1
1.2
1.3
1-1
PCI Mode Pin Descriptions ..........................................................................................1-1
VL Mode Pin Descriptions............................................................................................1-6
I/O Registers................................................................................................................1-10
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
Configuration Registers........................................................................................1-10
Common Registers ..............................................................................................1-12
Active Count Function ..........................................................................................1-15
Recovery Count Function.....................................................................................1-15
Task File Registers ..............................................................................................1-16
1.4
Configuration Setup ...................................................................................................1-16
1.4.1
1.4.2
1.4.3
1.4.4
VL Mode...............................................................................................................1-16
PCI Mode Configuration.......................................................................................1-16
Configuration Mechanism #2 ...............................................................................1-16
VL-Mode Operation..............................................................................................1-17
1.5
1.6
1.7
PCI0640B Interrupt Processing on PCI .....................................................................1-17
Read Ahead Operation ...............................................................................................1-17
PCI0640B IDE Controller Pinout ................................................................................1-17
1.7.1
1.7.2
1.7.3
Host Interface Pinout............................................................................................1-17
Drive Interface Pinout...........................................................................................1-19
VDD/VSS Pins .....................................................................................................1-20
1.8
Jumper Settings..........................................................................................................1-20
2
Power Specifications
2.1
2-1
DC Specifications .........................................................................................................2-1
2.1.1
2.1.2
Maximum Ratings ..................................................................................................2-1
Recommended Operating Conditions ....................................................................2-1
2.2
DC Characteristics........................................................................................................2-1
Table of Contents
0-iii
PCI0640B
2.3
AC Specifications .........................................................................................................2-2
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
Timing Waveform ...................................................................................................2-2
Clock Timing ..........................................................................................................2-2
Host Interface Timing (loading = 50 pf) ..................................................................2-2
IDE Drive Timing (loading = 75 pf) .........................................................................2-3
IDE Drive Timing (loading = 120 pf) .......................................................................2-3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Output Test Load ..........................................................................................................2-3
IDE Write Timing ...........................................................................................................2-4
Host Read/Write Timing ...............................................................................................2-4
VCLK, RESET# Timing .................................................................................................2-5
PCI Host Timing ............................................................................................................2-6
VL Mode Timing ............................................................................................................2-7
IDE Timing ...................................................................................................................2-8
A Diagrams
A-1
0-iv
Table of Contents
1 Interface Specifications
1.1 PCI Mode Pin Descriptions
The following is an alphabetical listing of PCI mode signals and their pin assignments. Please refer to the
PCI mode pinout diagram for the locations of the pins.
Signal
AD[31..0]
Function
Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase
followed by one or more data phases. PCI supports both read and write bursts. The address phase is the clock
cycle in which FRAME # is asserted. During the address phase AD[31..0] contain a physical address (32 bits).
For I/O, this is a byte address; for configuration and memory it is a DWORD address. During data phases
AD[7..0] contain the least significant byte (lsb) and AD[31..24] contain the most significant byte (msb). Write
data are stable and valid when IRDY# is asserted and read data are stable and valid when TRDY# is asserted.
Data are transferred during those clocks where both IRDY# and TRDY# are asserted.
Pin
7-14, 17-20, 23-26, 28-35, 42-49
I/O
IO
Signal
C/BE[3..0]#
Function
Pin
3-6
I/O
I
Byte Enable bits 0 through 3 form the host CPU address bus. These inputs are active low and specify which
bytes will be valid for host read/write data transfers.
Signal
DCS0#
Function
Pin
55
I/O
IO
Disk Chip Select 0 is normally active low output and is used to select the first IDE port command block
registers in the drive(s). This signal connects directly to the ATA bus connector. DCS0# is used as an input at
reset to specify PCI0640B operating modes (see Jumper Settings on page 1-20). DCS0# is sampled as an
input on the rising edge of RESET#. This pin is internally pulled up.
Signal
DCS1#
Function
Pin
56
I/O
IO
Disk Chip Select 1 is normally active low output which is used to select the first IDE port auxiliary registers in
the drive(s). This signal connects directly to the ATA bus connector. DCS1# is used as an input at reset to
specify PCI0640B operating modes (see Jumper Settings on page 1-20). DCS1# is sampled as an input on the
rising edge of RESET#. This pin is internally pulled up.
Interface Specifications
1-1
模拟电子
