MAN-00646U-000
Rev. 0.9
April 21, 1997
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PCI0646U
Bus Master Ultra DMA
PCI-IDE Chip Specification
CMD Technology, Inc.
1 Vanderbilt
Irvine, California 92618
(714) 454-0800
Revision History
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Revision
0.8
0.9
Date
3/3/97
4/22/97
Comments
First internal release
Revision
Table of Contents
1
2
MAN-00646U-000
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1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
2.1
2.2
2.3
PCI0646U Chip Specifications............................................................................. 1
Pin Descriptions ............................................................................................. 1
(1) Standard Configuration Header ....................................................................... 9
(2) Base Address Registers................................................................................... 9
Register Definition.......................................................................................... 9
Status/Command Register (04h).....................................................................10
Configuration Registers .................................................................................11
IDE Timing Control Registers .........................................................................11
PCI Master Control Registers .........................................................................15
Active Count Function....................................................................................20
Recovery Count Function ...............................................................................21
Task File Registers........................................................................................21
Configuration Setup .....................................................................................22
Notes: .................................................................................................................. 22
Configuration Mechanism #2 ............................................................................... 22
PIO Mode Interrupt Processing.....................................................................22
DMA Programming......................................................................................22
Read Ahead Operation ................................................................................22
Host Interface Pinout ........................................................................................... 23
Drive Interface Pinout .......................................................................................... 24
VDD/VSS Pins ..................................................................................................... 25
PCI0646U IDE Controller Pinout ...................................................................23
Jumper Settings ..........................................................................................27
Pinout Diagram (PQFP Package) .................................................................28
PCI0646U Power Specifications .........................................................................29
DC Specifications..........................................................................................29
Maximum Ratings ................................................................................................ 29
Recommended Operating Conditions (Vss = 0V) ................................................ 29
DC Characteristics.........................................................................................30
AC Specifications ..........................................................................................30
iii
Rev. 0.9
MAN-00646U-000
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2.4
2.5
2.6
2.7
2.8
2.9
2.10
Timing Waveform................................................................................................. 30
Clock Timing........................................................................................................ 31
Host Interface Timing (loading = 50 pf) ............................................................... 31
IDE Drive Timing (loading = 75 pf) ...................................................................... 31
IDE Drive Timing (loading = 120 pf) .................................................................... 32
Output Test Load...........................................................................................32
IDE Write Timing...........................................................................................33
Host Read/Write Timing.................................................................................33
PCI Read/Write Timing in Target Mode...........................................................34
IDE Timing....................................................................................................35
PCI DMA Master Read Timing (33MHz PCICLK).............................................36
PCI DMA Master Write Timing (33MHz PCICLK) ...........................................37
iv
1.1 Pin Descriptions
The following is an alphabetical listing of signals and their pin assignments. A numerically sorted pinout begins on page 23.
Please refer to the pinout diagram for the locations of the pins.
Signal
2NDIDEEN#/
DMACK0#
Function
Pin
87
Type
This signal normally is used in response to DMARQ0 to either acknowledge that data has been accepted, or that data
is available. At power-up reset, the state of this signal is used to enable or disable the secondary channel.
Signal
2NDIOR#/
2NDHDMARDY#/
2NDHSTROBE
Function
Secondary Channel Disk I/O Read is an active low output which enables data to be read from the drive. The duration
and repetition rate of DIOR# cycles is determined by PCI0646U programming. DIOR# is driven high when inactive.
This signal is defined as HSTROBE in Ultra DMA write mode to write data to the secondary channel drive. This signal
is also defined as secondary channel HDMARDY# in Ultra DMA read mode.
Signal
2NDIOW#/
2NDSTOP
Function
Pin
78
Seondary Channel Disk I/O Write is an active low output that enables data to be written to the drive. The duration and
repetition rate of DIOW# cycles is determined by PCI0646U programming. DIOW# is driven high when inactive. This
signal is defined as secondary channel STOP in Ultra DMA mode.
PCI0646U Chip Specifications
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B/T
Pin
77
1 PCI0646U Chip Specifications
Type
T/O
Type
T/O
1
