INTEGRATED CIRCUITS
PCK2022R
CK00 (100/133 MHz) spread spectrum
differential system clock generator
Product specification
Supersedes data of 2000 Aug 08
2000 Nov 13
Philips
Semiconductors
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum
differential system clock generator
PCK2022R
FEATURES
•
3.3 V operation
•
Eight differential CPU clock pairs
•
One IO clock at 33 MHz and 66 MHz
•
Two 48 MHz clocks at 3.3 V
•
One 14.318 MHz reference clock
•
Power management control pins
•
Host clock jitter less than 200 ps cycle-to-cycle
•
Host clock skew less than 150 ps pin-to-pin
•
Spread Spectrum capability
DESCRIPTION
The PCK2022R is a clock synthesizer/driver for a Pentium III™ and
other similar processors
The PCK2022R has eight differential pair CPU current source
outputs, one 33/66 MHz output which is configurable on power-up,
two 48 MHz clocks which can be disabled on power-up, and one
3.3 V reference clock at 14.318 MHz which can also be disabled on
power-up. All clock outputs meet Intel’s drive strength, rise/fall times,
jitter, accuracy, and skew requirements.
The part possesses a dedicated power-down input pin for power
management control. This input is synchronized on chip, and
ensures glitch-free output transitions. In addition, the part can be
configured to disable the 48 MHz outputs for lower power operation
and an increase in the performance of the functioning outputs. The
IOCLK and REFCLK can also be disabled for the highest
performance of the Host outputs.
PIN CONFIGURATION
IOCLK
V
DD
48M_0/SELA
48M_1/SELB
V
SS
V
DD
HCLK0
HCLKB0
V
SS
1
2
3
4
5
6
7
8
9
48 SEL100/133
47 V
SS
46 V
DDA
45 V
SSA
44 PWRDWN
43 V
DD
42 HCLK4
41 HCLKB4
40 V
SS
39 HCLK5
38 HCLKB5
37 V
DD
36 HCLK6
35 HCLKB6
34 V
SS
33 HCLK7
32 HCLKB7
31 V
DD
30 MULTSEL0
29 MULTSEL1
28 V
SS
27 V
SSA
26 I
REF
25 V
DDA
HCLK1 10
HCLKB1 11
V
DD
12
HCLK2 13
HCLKB2 14
V
SS
15
HCLK3 16
HCLKB3 17
V
DD
18
REFCLK/SELC 19
SPREAD 20
V
SS
21
XIN 22
XOUT 23
V
DD
24
SW00665
ORDERING INFORMATION
PACKAGES
48-Pin Plastic TSSOP
TEMPERATURE RANGE
0°C to +70°C
ORDER CODE
PCK2022R DGG
DRAWING NUMBER
SOT362-1
Intel and Pentium III are trademarks of Intel Corporation.
2000 Nov 13
2
853–2225 25005
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
PIN DESCRIPTION
PIN(S)
1
3, 4
7, 8
10, 11
13, 14
16, 17
42, 21
39, 38
36, 35
33, 32
19
20
21
22
26
29, 30
44
48
2, 6, 12,
18, 24, 31,
37, 43
5, 9, 15,
21, 28, 34,
40, 47
25, 46
27, 45
SYMBOL
IOCLK
48M_0/SELA
48M_1/SELB
HCLK0
HCLKB0
HCLK1
HCLKB1
HCLK2
HCLKB2
HCLK3
HCLKB3
HCLK4
HCLKB4
HCLK5
HCLKB5
HCLK6
HCLKB6
HCLK7
HCLKB7
REFCLK/SELC
SPREAD
XIN
XOUT
I
REF
MULTSEL0
MULTSEL1
PWRDWN
SEL100/133
V
DD3
FUNCTION
Dual frequency pin which can operate at either 33 MHz or 66 MHz per the selection table.
3.3 V fixed 48 MHz clock outputs. During power-up pins function as latched inputs that enable SELA and
SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in.
Host output pair 0
Host output pair 1
Host output pair 2
Host output pair 3
Host output pair 4
Host output pair 5
Host output pair 6
Host output pair 7
3.3 V fixed 14.318 MHz output. During power-up, pin functions as a latched input that enables SELC prior
to the pin being used for the clock output. Part must be clocked to latch data in.
Enables spread spectrum mode when held LOW on differential host outputs and 33 MHz IOCLK clocks.
Asserts LOW.
Crystal input
Crystal output
This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the correct current.
Select input pin used to control the scaling of the HCLK and HCLKB output current.
Device enters power-down mode when held LOW. Asserts LOW.
Select input pin for enabling 133 MHz or 100 MHz CPU outputs
3.3 V power supply
GND
Ground
AV
DD
AGND
3.3 V power supply for analog circuits
Ground for analog circuits
2000 Nov 13
3
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
BLOCK DIAGRAM
PWRDWN
XIN
14.318 MHz
OSC
USB PLL
PWRDWN
SELA/B
PWRDWN
SELC
REF[0] (14.318 MHz)
XOUT
48MHz[0..1] (3 V)
HOST[0..7] (100/133 MHz)
I
REF
IBIAS
PWRDWN
SYS PLL
HOST_BAR[0..7] (100/133 MHz)
PWRDWN
IOCLK (33/66 MHz)
PWRDWN
SEL100/133
LOGIC
SPREAD
MULTSEL0
MULTSEL1
SW00666
FUNCTION TABLE
SEL100/133
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SELA
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SELB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SELC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HOST
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
Low
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
200 MHz
133 MHz
TCLK/2
133 MHz
48MHz
48 MHz
48 MHz
Hi-Z
Hi-Z
Hi-Z
48 MHz
1
Hi-Z
48 MHz
1
48 MHz
48 MHz
Hi-Z
Hi-Z
48 MHz
48 MHz
1
TCLK/4
48 MHz
1
IOCLK
33.3 MHz
66.7 MHz
33.3 MHz
66.7 MHz
Low
33.3 MHz
Hi-Z
66.7 MHz
33.3 MHz
66.7 MHz
33.3 MHz
66.7 MHz
33.3 MHz
33.3 MHz
TCLK/4
66.7 MHz
REFCLK
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Low
14.318 MHz
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
14.318 MHz
NOTE:
1. These frequencies are for debug, and thus can vary a small amount from the values listed at the vendor’s discretion.
2000 Nov 13
4
Philips Semiconductors
Product specification
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2022R
Table 1. Host swing select functions
MULTSEL0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MULTSEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BOARD
IMPEDANCE
60
Ω
50
Ω
60
Ω
50
Ω
60
Ω
50
Ω
60
Ω
50
Ω
30
Ω
25
Ω
30
Ω
25
Ω
30
Ω
25
Ω
30
Ω
25
Ω
I
REF
R
REF
= 475 1%
I
REF
= 2.32 mA
R
REF
= 475 1%
I
REF
= 2.32 mA
R
REF
= 475 1%
I
REF
= 2.32 mA
R
REF
= 475 1%
I
REF
= 2.32 mA
R
REF
= 475 1%
I
REF
= 2.32 mA
R
REF
= 475 1%
I
REF
= 2.32 mA
R
REF
= 475 1%
I
REF
= 2.32 mA
R
REF
= 475 1%
I
REF
= 2.32 mA
R
REF
= 221 1%
I
REF
= 5 mA
R
REF
= 221 1%
I
REF
= 5 mA
R
REF
= 221 1%
I
REF
= 5 mA
R
REF
= 221 1%
I
REF
= 5 mA
R
REF
= 221 1%
I
REF
= 5 mA
R
REF
= 221 1%
I
REF
= 5 mA
R
REF
= 221 1%
I
REF
= 5 mA
R
REF
= 221 1%
I
REF
= 5 mA
I
OH
I
OH
= 5*I
REF
I
OH
= 5*I
REF
I
OH
= 6*I
REF
I
OH
= 6*I
REF
I
OH
= 4*I
REF
I
OH
= 4*I
REF
I
OH
= 7*I
REF
I
OH
= 7*I
REF
I
OH
= 5*I
REF
I
OH
= 5*I
REF
I
OH
= 6*I
REF
I
OH
= 6*I
REF
I
OH
= 4*I
REF
I
OH
= 4*I
REF
I
OH
= 7*I
REF
I
OH
= 7*I
REF
V
OH
@ IREF = 2.32 mA
0.71 V
0.59 V
0.85 V
0.71 V
0.56 V
0.47 V
0.99 V
0.82 V
0.75 V
0.62 V
0.90 V
0.75 V
0.60 V
0.50 V
1.05 V
0.84 V
NOTE:
The outputs are optimized for the configurations shown shaded.
CONDITIONS
I
OUT
I
OUT
V
DD
= 3.3 V
V
DD
= 3.3 V
±5%
CONFIGURATION
All combinations;
see Table 1 above
All combinations;
see Table 1 above
LOAD
Nominal test load for
given configuration
Nominal test load for
given configuration
MIN.
–7% of I
OH
see Table 1 above
–12% of I
OH
see Table 1 above
MAX.
+7% of I
OH
see Table 1 above
+12% of I
OH
see Table 1 above
POWER-DOWN MODE
PWRDWN
Asserts LOW
0 = Active
HCLK/HCLKB
Host = 2*I
REF
Host_bar = undriven
IOCLK
LOW
48MHz
LOW
REFCLK
LOW
NOTE:
The differential outputs should have a voltage forced across them when power-down is asserted.
SPREAD SPECTRUM FUNCTION
SPREAD #
1
0
FUNCTION
Host/IOCLK
No Spread
Host/IOCLK
Down spread –0.5%
5
48 MHz PLL
REFCLK
No Spread
No Spread
2000 Nov 13
