advanced CMOS technology. The device consists of two
banks of drivers, each with a 1:5 fanout and its own output
enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to
all other outputs and complies with the output specifications
in this document. The PCS2P3805E offers low capacitance
inputs. The PCS2P3805E is designed for high speed clock
distribution where signal quality and skew are critical. The
PCS2P3805E also allows single point-to-point transmission
line driving in applications such as address distribution,
where one signal must be distributed to multiple receivers
with low skew and high signal quality.
Block Diagram
Pin Diagram
OE
A
IN
A
5
OA
1
– OA
5
V
CCA
OA
1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
V
CCB
OB
1
OB
2
OB
3
GND
B
OB
4
OB
5
MON
OE
B
IN
B
OA
2
OA
3
GND
A
PCS2P3805E
16
15
14
13
12
11
IN
B
OE
B
5
OB
1
– OB
5
OA
4
OA
5
GND
Q
MON
OE
A
IN
A
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006
rev 0.3
Pin Description
Pin #
9,12
10,11
2,3,4,6,7
19,18,17,15,14
1
20
5
16
8
13
PCS2P3805E
Pin Names
OE
A
, OE
B
¯¯ ¯¯
IN
A
, IN
B
OA
1
-OA
5
OB
1
-OB
5
V
CCA
V
CCB
GND
A
GND
B
GND
Q
MON
Description
3-State Output Enable Inputs (Active LOW)
Clock Inputs
Clock Outputs from Bank A
Clock Outputs from Bank B
Power supply for Bank A
Power supply for Bank B
Ground for Bank A
Ground for Bank B
Ground
Monitor Output
Function Table
1
Inputs
OE
A
, OE
B
¯¯ ¯¯
L
L
H
H
Note: 1 H = HIGH; L = LOW; Z = High-Impedance
Outputs
IN
A
, IN
B
L
H
L
H
OA
n
, OB
n
L
H
Z
Z
MON
L
H
L
H
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
1
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
3
-
Max
4
6
Unit
pF
pF
Note: 1 This parameter is measured at characterization but not tested.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
2 of 11
September 2006
rev 0.3
Absolute Maximum Ratings
1
Symbol
V
CC
V
I
V
O
T
J
T
STG
T
DV
PCS2P3805E
Description
Input Power Supply Voltage
Input Voltage
Output Voltage
Junction Temperature
Storage Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Max
-0.5 to +4.6
-0.5 to +5.5
-0.5 to V
CC
+0.5
150
-65 to +165
2
Unit
V
V
V
°C
°C
KV
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics over Operating Range
Following Conditions Apply Unless Otherwise Specified
Industrial: T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
I
OS
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Outputs Pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Short Circuit Current
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.
Test Conditions
1
Min
2
-0.5
Typ
2
-
-
-
-
-
-
-0.7
-74
90
-135
3
3
-
0.3
0.2
-
Max
5.5
0.8
±1
±1
±1
±1
-1.2
-180
200
-240
-
-
-
0.4
0.4
0.2
Unit
V
V
V
I
= 5.5V
V
I
= GND
V
O
= V
CC
V
O
= GND
-
-
-
-
-
-45
50
-60
µA
V
CC
= Min., I
IN
= –18mA
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
3,4
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
3,4
V
CC
= Max., V
O
= GND
V
CC
= Min.
V
IN
= V
IH
or V
IL
3,4
V
mA
mA
mA
I
OL
= 12mA
V
OH
Output HIGH Voltage
I
OH
= –8mA
I
OH
= –100µA
I
OL
= 12mA
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 8mA
I
OL
= 100µA
2.4
5
2.4
5
V
CC
- 0.2
-
-
-
V
V
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, 25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
-0.6V at rated current.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
3 of 11
September 2006
rev 0.3
Power Supply Characteristics
Symbol
I
CCL
I
CCH
I
CCZ
∆I
CC
I
CCD
PCS2P3805E
Parameter
Quiescent Power Supply
Current
Power Supply Current per
Input HIGH
Test Conditions
1
V
CC
= Max. V
IN
= GND or V
CC
V
CC
= Max.
V
IN
= V
CC
–0.6V
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
–0.6V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
–0.6V
V
IN
= GND
Min
-
-
-
Typ
2
0.1
45
80
Max
30
300
120
Unit
µA
µA
µA/MHz
V
CC
= Max.
Dynamic Power Supply
C
L
= 15pF
3
Current per Output
All Outputs Toggling
V
CC
= Max.
C
L
= 15pF
All Outputs Toggling
f
i
= 133MHz
V
CC
= Max.
C
L
= 15pF
All Outputs Toggling
f
i
= 166MHz
-
-
-
-
210
210
260
260
240
240
mA
310
310
I
C
Total Power Supply
4
Current
Notes:
1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
4. I
C
= IQUIESCENT + IINPUTS + IDYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
O
N
O
)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= V
CC
-0.6V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
O
= Output Frequency
NO = Number of Outputs at f
O
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
4 of 11
September 2006
rev 0.3
Switching Characteristics Over Operating Range – PCS2P3805E
3,4
Symbol
t
PLH
t
PHL
t
R
t
F
t
SK(O)
t
SK(P)
t
SK(PP)
t
PZL
t
PZH
t
PLZ
t
PHZ
f
MAX
PCS2P3805E
Parameter
Propagation Delay
IN
A
to OA
n
, INB to OB
n
Output Rise Time
(Measured from 0.7V to 1.7V)
Output Fall Time
(Measured from 1.7V to 0.7V)
Same device output pin to pin skew
5
Pulse skew
6,9
Part to part skew
7
Output Enable Time
¯¯
¯¯
OE
A
to OA
n
, OE
B
to OB
n
Output Disable Time
¯¯
¯¯
OE
A
to OA
n
, OE
B
to OB
n
Input Frequency
Conditions
1,8
Min
2
0.5
-
-
-
Max
2.5
1
1
200
270
550
5.2
5.2
166
Unit
nS
nS
nS
pS
pS
pS
nS
nS
MHz
C
L
= 15pF
f
≤166MHz
-
-
-
-
-
Notes:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
PLH ,
t
PHL
and t
SK(O)
are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min and Max limit is due to V
CC
, operating temperature and process parameters. These propagation delay limits do not
imply skew.
5. Skew measured between all outputs under identical transitions and load conditions.
6. Skew measured is difference between propagation delay times t
PHL
and t
PLH
of same outputs under identical load conditions.
7. Part to part skew for all outputs given identical transitions and load conditions at identical V
CC
levels and temperature.
8. Airflow of 1m/s is recommended for frequencies above 133MHz.
9. This parameter is measured using f = 1MHz.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
