The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
PCBs, etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating the clock frequency. The PCS3P624Z05/09
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below the reference frequency with a specified
modulation rate. With center modulation, the average
frequency is the same as the unmodulated frequency and
there is no performance degradation.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the DLY_CTRL
pin is the internal feedback to the PLL, its relative loading
can adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including DLY_CTRL, must be equally loaded.
Even if DLY_CTRL is not used, it must have a capacitive
load equal to that on other outputs, for obtaining zero
input-output delay.
Timing-Safe™ technology
Timing-Safe™ technology is the ability to modulate a
clock source with Spread Spectrum technology and
maintain synchronization with any associated data path.
Rev. #1 | Page 2 of 15 | www.onsemi.com
PCS3P624Z05B/C and PCS3P624Z09B/C
Pin Configuration for PCS3P624Z05B/C
CLKIN
1
CLKOUT1
2
CLKOUT2
3
GND
4
PCS3P624Z05B/C
8
DLY_CTRL
CLKOUT4
VDD
CLKOUT3
7
6
5
Pin Description for PCS3P624Z05B/C
Pin #
1
2
3
4
5
6
7
8
Pin Name
CLKIN
1
2
2
Type
I
O
O
P
O
P
O
O
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
4
4
4
4
Description
External reference Clock input, 5V tolerant input
CLKOUT1
CLKOUT2
GND
CLKOUT3
VDD
CLKOUT4
2
2
DLY_CTRL
External Input-Output Delay control. This pin can be used as clock output
4
Notes: 1. Weak pull down
2. Weak pull-down on all outputs
3. Weak pull-up on these Inputs
4. Buffered clock output is Timing-Safe™
Rev. #1 | Page 3 of 15 | www.onsemi.com
PCS3P624Z05B/C and PCS3P624Z09B/C
Pin Configuration for PCS3P624Z09B/C
CLKIN
1
CLKOUTA1
2
CLKOUTA2
3
VDD
4
GND
5
16
15
14
13
DLY_CTRL
CLKOUTA4
CLKOUTA3
VDD
GND
CLKOUTB4
CLKOUTB3
S1
PCS3P624Z09B/C
12
11
10
9
CLKOUTB1
6
CLKOUTB2
7
S2
8
Pin Description for PCS3P624Z09B/C
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
1
2
2
Pin Type
I
O
O
P
P
Buffered clock Bank A output
Buffered clock Bank A output
3.3V supply
Ground
Buffered clock Bank B output
Buffered clock Bank B output
4
4
4
4
Description
External reference Clock input, 5V tolerant input
CLKOUTA1
CLKOUTA2
VDD
GND
CLKOUTB1
CLKOUTB2
S2
S1
3
3
2
2
O
O
I
I
Select input, bit 2.See
Select Input Decoding table for PCS3P624Z09
for more details
Select input, bit 1.See
Select Input Decoding table for PCS3P624Z09
for more details
Buffered clock Bank B output
Buffered clock Bank B output
Ground
3.3V supply
Buffered clock Bank A output
Buffered clock Bank A output
4
4
4
4
CLKOUTB3
CLKOUTB4
GND
VDD
CLKOUTA3
CLKOUTA4
DLY_CTRL
2
2
O
O
P
P
2
2
O
O
O
2
External Input-Output Delay control. This pin can be used as clock output
Notes: 1. Weak pull down
2. Weak pull-down on all outputs
3. Weak pull-up on these Inputs
4. Buffered clock output is Timing-Safe™
Rev. #1 | Page 4 of 15 | www.onsemi.com
PCS3P624Z05B/C and PCS3P624Z09B/C
Select Input Decoding table for PCS3P624Z09
S2
0
0
1
1
S1
0
1
0
1
CLKOUT A1 - A4 CLKOUT B1 - B4 DLY_CTRL
Three-state
Driven
Driven
Driven
Three-state
Three-state
Driven
Driven
Driven
Driven
Driven
Driven
1
Output Source
PLL
PLL
Reference
PLL
PLL
Shut-Down
N
N
Y
N
Notes: This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and
the Output.
Spread Spectrum Control and Input-Output Skew Table
Frequency (MHz)
75
Device
PCS3P624Z05B / 09B
PCS3P624Z05C / 09C
Deviation (
±%)
0.25
0.5
Input-Output Skew (±T
SKEW
)
0.0625
0.125
Note: T
SKEW
is measured in units of the Clock Period
Absolute Maximum Ratings
Symbol
VDD
VIN
T
STG
T
s
T
J
T
DV
DC Input Voltage (CLKIN)
Storage temperature
Parameter
Rating
-0.5 to +4.6
-0.5 to +7
-65 to +125
260
150
2
Unit
V
°C
°C
°C
KV
Supply Voltage to Ground Potential
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
FPGA/CPLD
