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April 1
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD168302
MONOLITHIC 2CH H-BRIDGE DRIVER
DESCRIPTION
The
µ
PD168302 is monolithic dual H-bridge driver LSI which uses power MOS FETs in the output stages. By using
the MOS process, this driver has substantially improved the voltage loss of the output stage and power consumption
as compared with conventional driver using bipolar transistors.
As the package, a 24-pin plastic TSSOP is adopted to enable the creation of compact, slim application sets.
It is provided with forward/reverse and brake functions and is ideal as a driver for DC motor and stepping motor.
FEATURES
•
2ch H-Bridge circuit employing power MOS FETs
•
Charge-pump circuit for low-voltage operation
•
Low output FET on resistance: 1.0
Ω
TYP. 2.0
Ω
MAX. (Sum of upper and lower side)
•
Output current: DC current 0.6 A/ch
Peak current 1.0 A/ch
•
Input logic frequency: 100 kHz
•
5 V logic power supply: Minimum operating supply voltage 4.0 V
•
0.9 to 3.6 V power supply for motor drive
•
Under voltage locked out circuit: shutdown internal circuit at V
DD
= 1.7 V TYP.
•
24-pin plastic TSSOP (5.72 mm (225), 0.5 mm pitch)
ORDERING INFORMATION
Part Number
Package
24-pin plastic TSSOP (5.72 mm (225))
µ
PD168302MA-6A5
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16402EJ1V0DS00 (1st edition)
Date Published May 2003 NS CP (K)
Printed in Japan
2003
µ
PD168302
1. BLOCK DIAGRAM
V
DD
UVLO
Oscillator
Circuit
Charge-pump
Circuit
BGR
Circuit
/STB
Note2
IN1
Note2
C
1H
C
1L
C
2H
C
2L
V
G
V
M
Note3
V
M1
Note3
IN2
Note2
Control
Circuit
Level Shift
Circuit
MOS
H-bridge
Circuit 1
OUT1A
OUT1B
IN3
Note2
IN4
Note2
Control
Circuit
Level Shift
Circuit
MOS
H-bridge
Circuit 2
OUT2A
OUT2B
V
M2
Note3
LGND
PGND1
Note1, 4
PGND2
Note1, 4
Notes 1.
The terminal which has more than one should connect not only one terminal but all terminals.
2.
Pull down resistance (50 to 200 kΩ) is connected to the input terminal.
3.
It is recommended that V
M
terminal is connected to the terminal which either V
M1
or V
M2
is higher.
4.
It is recommended that the voltage of PGND1 and PGND2 is not lower value than GND.
2
Data Sheet S16402EJ1V0DS
µ
PD168302
2. PIN CONNECTION
C
1L
C
1H
V
G
V
DD
PGND1
OUT1A
V
M1
OUT1B
PGND1
/STB
IN1
IN2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
C
2L
C
2H
V
M
LGND
PGND2
OUT2A
V
M2
OUT2B
PGND2
N.C.
IN3
IN4
3. PIN FUNCTIONS
PACKAGE: 24-pin plastic TSSOP (5.72 mm (225), 0.5 mm pitch)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin Name
C
1L
C
1H
V
G
V
DD
PGND1
OUT1A
V
M1
OUT1B
PGND1
/STB
IN1
IN2
IN4
IN3
N.C.
PGND2
OUT2B
V
M2
OUT2A
PGND2
LGND
V
M
C
2L
C
2H
Pin Function
Capacitor connect pin for charge-pump circuit
Capacitor connect pin for charge-pump circuit
Gate voltage pin
Power supply pin for logic circuit
Power GND pin
Output A pin for ch1
Power supply pin for power circuit
Output B pin for ch1
Power GND pin
Standby pin
Input logic 1 pin for ch1
Input logic 2 pin for ch1
Input logic 4 pin for ch2
Input logic 3 pin for ch2
(No connect)
Power GND pin
Output B pin for ch2
Power supply pin for power circuit
Output A pin for ch2
Power GND pin
Logic GND pin
Power supply pin for power circuit
Capacitor connect pin for charge-pump circuit
Capacitor connect pin for charge-pump circuit
Cautions 1. The terminal which has more than one should connect not only one terminal but terminals.
2. Please recommend connecting unused pins to GND.
Data Sheet S16402EJ1V0DS
3
