PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD45128441-I, 45128841-I, 45128163-I
128M-bit Synchronous DRAM
4-bank, LVTTL
WTR (Wide Temperature Range)
Description
The
µ
PD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608
×
4
×
4, 4,194,304
×
8
×
4, 2,097,152
×
16
×
4 (word
×
bit
×
bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
•
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
•
Pulsed interface
•
Possible to assert random column address in every cycle
•
Quad internal banks controlled by BA0(A13) and BA1(A12)
•
Byte control (×16) by LDQM and UDQM
•
Programmable Wrap sequence (Sequential / Interleave)
•
Programmable burst length (1, 2, 4, 8 and full page)
•
Programmable /CAS latency (2 and 3)
•
Ambient temperature (T
A
):
−40
to + 85°C
•
Automatic precharge and controlled precharge
•
CBR (Auto) refresh and self refresh
• ×4, ×8, ×16
organization
•
Single 3.3 V
±
0.3 V power supply
•
LVTTL compatible inputs and outputs
•
4,096 refresh cycles / 64 ms
•
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0233N10 (Ver. 1.0)
Date Published November 2001 (K) Japa
C
Elpida Memory, Inc. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
µ
PD45128441-I, 45128841-I, 45128163-I
Ordering Information
Part number
Organization
(word
×
bit
×
bank)
8M
×
4
×
4
Clock frequency
MHz (MAX.)
133
125
100
4M
×
8
×
4
133
125
100
2M
×
16
×
4
133
125
100
8M
×
4
×
4
133
125
100
4M
×
8
×
4
133
125
100
2M
×
16
×
4
133
125
100
Package
Note
µ
PD45128441G5-A75I-9JF
µ
PD45128441G5-A80I-9JF
µ
PD45128441G5-A10I-9JF
µ
PD45128841G5-A75I-9JF
µ
PD45128841G5-A80I-9JF
µ
PD45128841G5-A10I-9JF
µ
PD45128163G5-A75I-9JF
µ
PD45128163G5-A80I-9JF
µ
PD45128163G5-A10I-9JF
µ
PD45128441G5-A75LI-9JF
µ
PD45128441G5-A80LI-9JF
µ
PD45128441G5-A10LI-9JF
µ
PD45128841G5-A75LI-9JF
µ
PD45128841G5-A80LI-9JF
µ
PD45128841G5-A10LI-9JF
µ
PD45128163G5-A75LI-9JF
µ
PD45128163G5-A80LI-9JF
µ
PD45128163G5-A10LI-9JF
54-pin Plastic TSOP (II) Ambient temperature
(10.16mm (400))
T
A
=
−40
to + 85°C
2
Preliminary Data Sheet E0233N10
µ
PD45128441-I, 45128841-I, 45128163-I
Part Number
[ x4, x8 ]
µ
PD45128841G5 - A75L I
NEC Memory
Synchronous DRAM
Memory density
128 : 128M bits
Wide temperature
range
I : -40 to + 85°C
Low Power
Organization
4 : x4
8 : x8
Minimum cycle time
75
80
10
: 7.5 ns (133 MHz)
: 8 ns (125 MHz)
: 10 ns (100 MHz)
Number of banks
4 : 4 banks
Interface
1 : LVTTL
Low voltage
A : 3.3 V
±
0.3 V
Package
[ x16 ]
Organization
16 : x16
Number of banks
and Interface
3 : 4 banks, LVTTL
163
G5 : TSOP (II)
Preliminary Data Sheet E0233N10
3
µ
PD45128441-I, 45128841-I, 45128163-I
Pin Configurations
/xxx indicates active low signal.
[
µ
PD45128441]
54-pin Plastic TSOP (II) (10.16mm (400))
8M words
×
4 bits
×
4 banks
V
CC
NC
V
CC
Q
NC
DQ0
V
SS
Q
NC
NC
V
CC
Q
NC
DQ1
V
SS
Q
NC
V
CC
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
NC
VssQ
NC
DQ3
VccQ
NC
NC
VssQ
NC
DQ2
VccQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
A0 to A11
Note
: Address inputs
: Data inputs / outputs
: Clock input
: Clock enable
: Chip select
: Row address strobe
: Column address strobe
: Write enable
: DQ mask enable
: Supply voltage
: Ground
: Supply voltage for DQ
: Ground for DQ
: No connection
Note
A0 to A11
: Row address inputs
A0 to A9, A11 : Column address inputs
BA0(A13), BA1(A12): Bank select
DQ0 to DQ3
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
4
Preliminary Data Sheet E0233N10
µ
PD45128441-I, 45128841-I, 45128163-I
[
µ
PD45128841]
54-pin Plastic TSOP (II) (10.16mm (400))
4M words
×
8 bits
×
4 banks
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ7
VssQ
NC
DQ6
VccQ
NC
DQ5
VssQ
NC
DQ4
VccQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
A0 to A11
Note
: Address inputs
: Data inputs / outputs
: Clock input
: Clock enable
: Chip select
: Row address strobe
: Column address strobe
: Write enable
: DQ mask enable
: Supply voltage
: Ground
: Supply voltage for DQ
: Ground for DQ
: No connection
Note
A0 to A11 : Row address inputs
A0 to A9 : Column address inputs
BA0(A13), BA1(A12): Bank select
DQ0 to DQ7
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Preliminary Data Sheet E0233N10
5
嵌入式系统
