Datasheet
μ
PD46365092B
μ
PD46365182B
μ
PD46365362B
36M-BIT QDR
TM
II SRAM
2-WORD BURST OPERATION
Description
The
μ
PD46365092B is a 4,194,304-word by 9-bit, the
μ
PD46365182B is a 2,097,152-word by 18-bit and the
μ
PD46365362B is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The
μ
PD46365092B,
μ
PD46365182B and
μ
PD46365362B integrate unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and
K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
R10DS0089EJ0400
Rev.4.00
Nov 09, 2012
Features
•
1.8 ± 0.1 V power supply
•
165-pin PLASTIC BGA (13 x 15)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Separate independent read and write data ports with concurrent transactions
•
100% bus utilization DDR READ and WRITE operation
•
Two-tick burst for low DDR transaction size
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 20
μ
s after clock is resumed.
•
User programmable impedance output (35 to 70
Ω)
•
Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz).
•
Simple control logic for easy depth expansion
•
JTAG 1149.1 compatible test access port
R10DS0089EJ0400 Rev.4.00
Nov 09, 2012
Page 1 of 35
μ
PD46365092B,
μ
PD46365182B,
μ
PD46365362B
Ordering Information
Organization
(word x bit)
4M x 9
2M x 18
1M x 36
4M x 9
2M x 18
1M x 36
4M x 9
2M x 18
1M x 36
4M x 9
2M x 18
1M x 36
Cycle
time
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
Clock
frequency
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
1.8
±0.1V
T
A
= -40 to 85°C
1.8
±0.1V
T
A
= 0 to 70°C
165-pin
PLASTIC
BGA
(13 x 15)
Lead
1.8
±0.1V
T
A
= -40 to 85°C
Core
Supply
Voltage
1.8
±0.1V
Operating
Ambient
Temperature
T
A
= 0 to 70°C
Part No.
Package
165-pin
PLASTIC
BGA
(13 x 15)
Lead-free
μ
PD46365092BF1-E33-EQ1-A
μ
PD46365092BF1-E40-EQ1-A
μ
PD46365182BF1-E33-EQ1-A
μ
PD46365182BF1-E40-EQ1-A
μ
PD46365362BF1-E33-EQ1-A
μ
PD46365362BF1-E40-EQ1-A
μ
PD46365092BF1-E33Y-EQ1-A
μ
PD46365092BF1-E40Y-EQ1-A
μ
PD46365182BF1-E33Y-EQ1-A
μ
PD46365182BF1-E40Y-EQ1-A
μ
PD46365362BF1-E33Y-EQ1-A
μ
PD46365362BF1-E40Y-EQ1-A
μ
PD46365092BF1-E33-EQ1
μ
PD46365092BF1-E40-EQ1
μ
PD46365182BF1-E33-EQ1
μ
PD46365182BF1-E40-EQ1
μ
PD46365362BF1-E33-EQ1
μ
PD46365362BF1-E40-EQ1
μ
PD46365092BF1-E33Y-EQ1
μ
PD46365092BF1-E40Y-EQ1
μ
PD46365182BF1-E33Y-EQ1
μ
PD46365182BF1-E40Y-EQ1
μ
PD46365362BF1-E33Y-EQ1
μ
PD46365362BF1-E40Y-EQ1
R10DS0089EJ0400 Rev.4.00
Nov 09, 2012
Page 2 of 35
μ
PD46365092B,
μ
PD46365182B,
μ
PD46365362B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD46365092B]
4M x 9
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
3
A
NC
NC
NC
Q5
NC
Q6
V
DD
Q
NC
NC
D7
NC
NC
Q8
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NC
NC/288M
6
K#
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/144M
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
D0 to D8
Q0 to Q8
R#
W#
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1.
×××#
indicates active LOW.
2.
Refer to
Package Dimensions
for the index mark.
3.
2A, 7A and 5B are expansion addresses : 2A for 72Mb
: 2A and 7A for 144Mb
: 2A, 7A and 5B for 288Mb
2A of this product can also be used as NC.
R10DS0089EJ0400 Rev.4.00
Nov 09, 2012
Page 3 of 35
μ
PD46365092B,
μ
PD46365182B,
μ
PD46365362B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD46365182B]
2M x 18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/144M
3
A
D9
D10
Q10
Q11
D12
Q13
V
DD
Q
D14
Q14
D15
D16
Q16
Q17
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW1#
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/288M
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/72M
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
A
D0 to D17
Q0 to Q17
R#
W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1.
×××#
indicates active LOW.
2.
Refer to
Package Dimensions
for the index mark.
3.
2A, 7A and 10A are expansion addresses
: 10A for 72Mb
: 10A and 2A for 144Mb
: 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0089EJ0400 Rev.4.00
Nov 09, 2012
Page 4 of 35
μ
PD46365092B,
μ
PD46365182B,
μ
PD46365362B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD46365362B]
1M x 36
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
Q27
D27
D28
Q29
Q30
D30
DLL#
D31
Q32
Q33
D33
D34
Q35
TDO
2
3
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW2#
BW3#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
BW1#
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DD
Q
D12
Q12
D11
D10
Q10
Q9
A
10
V
SS
/144M
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
SS
/288M NC/72M
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
V
DD
Q
D23
Q23
D24
D25
Q25
Q26
A
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
A
D0 to D35
Q0 to Q35
R#
W#
BW0# to BW3#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1.
×××#
indicates active LOW.
2.
Refer to
Package Dimensions
for the index mark.
3.
2A, 3A and 10A are expansion addresses
: 3A for 72Mb
: 3A and 10A for 144Mb
: 3A, 10A and 2A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0089EJ0400 Rev.4.00
Nov 09, 2012
Page 5 of 35
