PRELIMINARY
PDM31034
1 Megabit 3.3V Static RAM
128K x 8-Bit
Revolutionary Pinout
Features
n
Description
The PDM31034 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. Writing is
accomplished when the write enable (WE) and the
chip enable (CE) inputs are both LOW. Reading is
accomplished when WE remains HIGH and CE and
OE are both LOW.
The PDM31034 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31034 is available in a 32-pin 400 mil plas-
tic SOJ and 300 mil plastic SOJ, and a 32-pin plastic
TSOP (II) package in revolutionary pinout.
1
2
3
4
5
6
High-speed access times
Com’l: 9, 10, 12, 15 and 20 ns
Ind’l.: 12, 15 and 20 ns
Automotive: 15 and 20 ns
Low power operation (typical)
- PDM31034SA
Active: 200 mW
Standby: 15 mW
Single +3.3V (
±
0.3V) power supply
TTL-compatible inputs and outputs
Packages
Plastic SOJ (400 mil) - SO
Plastic SOJ (300 mil) - TSO
Plastic TSOP (II) - T
n
n
n
n
Functional Block Diagram
A8
Addresses
A0
I/O0
Input
Data
Control
I/O7
Column Address
Buffer
A16
Control
7
Row
Address
Buffer
Row
Decoder
Memory
Array
512 x 256 x 8
(1,048,576)
8
9
10
11
12
1
Column I/O
Column Decoder
CE
WE
OE
A9
Rev. 1.3
PRELIMINARY
PDM31034
SOJ
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A4
A5
A6
A7
OE
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A8
A9
A10
A11
A12
Pin Configuration
TSOP
Pin Description
Name
A16-A0
I/O7-I/O0
OE
WE
CE
NC
V
CC
V
SS
Description
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Input
No Connect
Power (+3.3V)
Ground
A3
A2
A1
A0
CE
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A4
A5
A6
A7
OE
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A8
A9
A10
A11
A12
A2
A1
A0
CE
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE
A16
A15
A14
A13
Truth Table
(1)
CE
L
L
L
H
OE
L
X
H
X
WE
H
L
H
X
I/O
D
OUT
D
IN
Hi-Z
Hi-Z
MODE
Read
Write
Output Disable
Standby
NOTE: 1. H = V
IH
, L = V
IL
, X = DON’T CARE
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
T
j
Rating
Terminal Voltage with Respect to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Maximum Junction Temperature
(2)
Com’l.
–0.5 to +4.6
–55 to +125
–55 to +125
900
50
125
Ind.
–0.5 to +4.6
–65 to +135
–65 to +150
900
50
125
Auto.
–0.5 to +4.6
–65 to +145
–65 to +150
900
50
125
Unit
V
°
C
°
C
mW
mA
°
C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-
culation should be of the form
: T
j
= T
a
+ P *
θ
ja
where T
a
is the ambient temperature, P
is average operating power and
θ
ja
the thermal resistance of the package. For this
product, use the following
θ
ja
values:
SOJ: 72
o
C/W
TSOP: 95
o
C/W
2
Rev. 1.3
PRELIMINARY
PDM31034
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Industrial
Commercial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
Min.
3.0
0
–40
–0
Typ.
3.3
0
25
25
Max.
3.6
0
85
70
Unit
V
V
°
C
°
C
1
2
3
DC Electrical Characteristics
(V
CC
= 3.3V
±
0.3V)
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
Test Conditions
V
CC
= Max., V
IN
= V
SS
to V
CC
V
CC
= Max.,
CE = V
IH
, V
OUT
= V
SS
to V
CC
Com’l/
Ind.
Com’l/
Ind.
Min.
–5
–5
–0.3
(1)
2.2
—
2.4
Max.
5
5
0.8
Vcc+0.3
0.4
—
Unit
µ
A
µ
A
V
V
V
V
4
5
6
7
NOTE:1.V
IL
(min) = –3.0V for pulse width less than 20 ns
Power Supply Characteristics
-9
(1)
Symbol Parameter
I
CC
Operating Current
CE = V
IL
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
≥
V
CC
– 0.2V
f=0
V
CC
= Max.,
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
5
5
5
5
5
5
10
5
5
10
mA
20
20
20
20
20
20
30
20
20
30
mA
Com’l.
125
-10
(1)
Com’l.
115
-12
-15
-20
Auto. Com’l Ind.
110
90
95
Auto.
110
Unit
mA
Com’l Ind. Com’l Ind.
110
115
100
105
8
9
10
11
12
3
NOTES: All values are maximum guaranteed values.
1. V
CC
= 3.3V + 5%
Rev. 1.3
PRELIMINARY
PDM31034
Capacitance
(1)
(T
A
= +25
°
C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max.
8
8
Unit
pF
pF
NOTE:1. This parameter is determined by device characterization but is not production tested.
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
2.5 ns
1.5V
1.5V
See Figures 1 and 2
+3.3V
317Ω
D
OUT
351Ω
30 pF
D
OUT
351Ω
+3.3V
317Ω
5 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
,
t
HZOE
)
4
Rev. 1.3
PRELIMINARY
PDM31034
Read Cycle No. 1
(4, 5)
t
RC
ADDR
1
DATA VALID
t
AA
t
OH
DOUT
PREVIOUS DATA VALID
2
3
Read Cycle No. 2
(2, 4, 6)
t
RC
ADDR
t
AA
t
ACE
CE1
CE2
t
LZCE
OE
t
LZOE
D
OUT
t
AOE
t
HZOE
DATA VALID
4
5
t
HZCE
6
7
8
AC Electrical Characteristics
Description
READ Cycle
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in low Z
(1,3)
Chip disable to output in high Z
(1,2,3)
Chip enable to power up time
(3)
Chip disable to power down time
(3)
Output enable access time
Output Enable to output in low Z
(1,3)
-9
Sym
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
0
5
0
9
5
0
3
3
5
0
-10
-12
-15
-20
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
9
9
9
3
3
6
0
10
6
0
6
7
12
7
0
8
10
10
10
3
3
7
0
15
8
0
9
12
12
12
3
3
8
0
20
9
15
15
15
3
3
9
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
10
11
12
5
Output disable to output in high Z
(1,3)
Rev. 1.3
模拟与混合信号
