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PDM31256SA12SOI

Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

器件类别:存储    存储   

厂商名称:IXYS

器件标准:  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
IXYS
零件包装代码
SOJ
包装说明
0.300 INCH, PLASTIC, SOJ-28
针数
28
Reach Compliance Code
compliant
ECCN代码
EAR99
最长访问时间
12 ns
JESD-30 代码
R-PDSO-J28
长度
18.415 mm
内存密度
262144 bit
内存集成电路类型
STANDARD SRAM
内存宽度
8
功能数量
1
端子数量
28
字数
32768 words
字数代码
32000
工作模式
ASYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
32KX8
封装主体材料
PLASTIC/EPOXY
封装代码
SOJ
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
并行/串行
PARALLEL
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
3.75 mm
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子形式
J BEND
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
7.62 mm
文档预览
PDM31256
3.3V 256K Static RAM
32K x 8-Bit
Features
n
1
2
3
4
5
6
Description
The PDM31256 is a high-performance CMOS static
RAM organized as 32,768 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
The PDM31256 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31256 is available in a 28-pin 300-mil
plastic SOJ and a 28-pin plastic TSOP (I).
High-speed access times
Com’l: 10, 12, 15 and 20ns
Ind’l: 12, 15 and 20ns
Low power operation (typical)
- PDM31256SA
Active: 200 mW
Standby: 15mW
Single +3.3V (±0.3V) power supply
TTL-compatible inputs and outputs
Packages
Plastic SOJ (300 mil) - SO
Plastic TSOP (I) - T
n
n
n
n
Functional Block Diagram
7
A
0
A
14
Decoder
Memory
Matrix
Addresses
8
9
10
11
12
I/O
0
I/O
7
• • • • •
Input
Data
Control
Column I/O
CE
WE
OE
Control
Rev. 3.3 - 4/29/98
1
PDM31256
Pin Configurations
TSOP
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A1
A2
SOJ
Pin Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Name
A14-A0
I/O7-I/O0
OE
WE
CE
V
CC
V
SS
Description
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Input
Power (+3.3V)
Ground
Truth Table
OE
X
L
X
H
WE
X
H
L
H
CE
H
L
L
L
I/O
Hi-Z
D
OUT
D
IN
Hi-Z
MODE
Standby
Read
Write
Output Disable
NOTE: 1. H = V
IH
, L = V
IL
, X = DON’T CARE
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
T
j
Rating
Terminal Voltage with Respect to Vss
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Maximum Junction Temperature
(2)
Com’l.
–0.5 to +4.6
–55 to +125
–55 to +125
1.0
50
125
Ind.
–0.5 to +4.6
–65 to +135
–65 to +150
1.0
50
145
Unit
V
°C
°C
W
mA
°C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
θ
ja
where T
a
is the ambient tempera-
ture, P is average operating power and
θ
ja
the thermal resistance of the package. For
this product, use the following
θ
ja
values:
SOJ: 78
o
C/W
TSOP: 112
o
C/W
2
Rev. 3.3 - 4/29/98
PDM31256
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Commercial
Industrial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
Min.
3.0
0
0
–40
Typ.
3.3
0
25
25
Max.
3.6
0
70
85
Unit
V
V
°C
°C
1
2
3
DC Electrical Characteristics
(V
CC
= 3.3V
±
0.3V)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Test Conditions
V
CC
= MAX., V
IN
= Vss to V
CC
V
CC
= MAX.,
CE = V
IH
, V
OUT
=
Vss to V
CC
Min.
–5
–5
Max.
5
5
Unit
µA
µA
4
5
6
7
V
IL
V
IH
V
OL
V
OH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 8 mA
V
CC
= Min.
I
OH
= –4 mA,
V
CC
= Min.
–0.3
(1)
2.2
2.4
0.8
Vcc+0.3
0.4
V
V
V
V
NOTE:1.V
IL
(min) = –3.0V for pulse width less than 20 ns.
Power Supply Characteristics
-10
Symbol Parameter
I
CC
Operating Current
CE = V
IL
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
V
CC
– 0.2V
f=0
V
CC
= Max.,
V
IN
V
CC
– 0.2V or
0.2V
10
10
15
10
15
10
15
10
15
mA
45
40
35
35
35
35
35
30
30
mA
Com’l.
140
-12
-15
-17
-20
Unit
mA
Com’l Ind. Com’l Ind. Com’l Ind. Com’l Ind.
130
130
120
120
120
120
110
110
8
9
10
11
12
3
NOTES: All values are maximum guaranteed values.
Rev. 3.3 - 4/29/98
PDM31256
Capacitance
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max.
8
8
Unit
pF
pF
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
2.5 ns
1.5V
1.5V
See Figures 1 and 2
+3.3V
+3.3V
319Ω
DATA
OUT
353Ω
30 pF
319Ω
DATA
OUT
353Ω
5 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
,
t
HZOE
)
Delta tAA - ns
5
4
3
2
1
0
0
Typical Delta tAA vs Capacitive Loading
30
60
90
120
Additional Lumped Capacitive Loading (pF)
Figure 3.
4
Rev. 3.3 - 4/29/98
PDM31256
Read Cycle No. 1
(1)
ADDR
t OH
t AA
DATA VALID
t RC
1
2
3
DOUT PREVIOUS DATA VALID
Read Cycle No. 2
(2)
t
RC
ADDR
t
AA
t
ACE
CE
4
t
HZCE
t
HZOE
DATA VALID
t
LZCE
OE
t
LZOE
D
OUT
5
6
t
AOE
AC Electrical Characteristics
Description
READ Cycle
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in low Z
(3,4,5)
Chip disable to output in high Z
(3,4,5)
Chip enable to power up time
(4)
Chip disable to power down time
(4)
Output enable access time
Output enable to output in low Z
(4,5)
Output disable to output in high Z
(4,5)
Sym
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
0
8
0
10
5
0
8
3
5
8
0
12
6
0
8
-10
-12
-15
-17
Max
Min
-20
Max
Units
ns
7
Min. Max. Min. Max. Min. Max. Min
10
10
10
3
5
10
0
15
8
12
12
12
3
5
10
15
15
15
17
17
17
3
5
12
0
17
9
0
8
20
20
20
3
5
15
0
20
10
0
8
8
9
10
11
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 3.3 - 4/29/98
5
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