PRELIMINARY
PDM31548
PDM31548
128K x 16 CMOS
3.3V Static RAM
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3
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5
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Features
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Description
The PDM31548 is a high-performance CMOS static
RAM organized as 131,072 x 16 bits. The PDM31548
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM31548 operates from a single 3.3V power
supply and all inputs and outputs are fully TTL-
compatible.
The PDM31548 is available in a 44-pin 400-mil plas-
tic SOJ and a plastic TSOP (II) package for high-
density surface assembly and is suitable for use in
high-speed applications requiring high-speed
storage.
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High-speed access times
- Com’l: 10, 12, 15 and 20 ns
- Ind: 12, 15 and 20 ns
Low power operation (typical)
- PDM31548SA
Active: 250 mW
Standby: 25 mW
High-density 128K x 16 architecture
3.3V (±0.3V) power supply
Fully static operation
TTL-compatible inputs and outputs
Output buffer controls: OE
Data byte controls: LB, UB
Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
Row Address
Buffer
Row Decoder
Vcc
Vss
A8-A0
Memory
Cell
Array
256 x
x
128 x 32
512 128 x 32
8
9
10
11
I/O15-I/O0
Data
Input/
Output
Buffer
Sense Amp
Column
Decoder
WE
OE
UB
LB
CE
Control
Logic
Clock
Generator
Column
Address
Buffer
12
A16 - A9
A15-A9
Rev. 1.3 - 4/13/98
1
PRELIMINARY
PDM31548
Pin Configuration
TSOP
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SOJ
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Pin Description
Name
A16-A0
I/O15-I/O0
CE
WE
OE
LB, UB
NC
V
ss
V
CC
Description
Address Inputs
Data Inputs
Chip Enable Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
No Connect
Ground
Power (+3.3V)
Capacitance
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= V
SS
V
I/O
= V
SS
Max.
6
8
Unit
pF
pF
NOTE:
1. This parameter is determined by device characterization, but is not production tested.
2
Rev. 1.3 - 4/13/98
PRELIMINARY
PDM31548
Operating Mode
Mode
Read
CE
L
OE
L
WE
H
LB
L
H
L
Write
L
X
L
L
H
L
Output Disable
L
L
Standby
H
H
X
X
H
X
X
X
H
X
UB
L
L
H
L
L
H
x
H
X
I/O7-I/O0
Output
High Impedance
Output
Input
High Impedance
Input
High Impedance
High Impedance
High Impedance
I/O15-I/O8
Output
Output
High Impedance
Input
Input
High Impedance
High Impedance
High Impedance
High Impedance
Power
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
SB
1
2
3
4
5
6
7
8
9
10
NOTE: 1. H = V
IH
, L = V
IL
, X = DON’T CARE
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
T
j
Rating
Terminal Voltage with Respect to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Maximum Junction Temperature
(2)
Com’l.
–0.5 to +4.6
–55 to +125
–55 to +125
1.5
50
125
Ind.
–0.5 to +4.6
–65 to +135
–65 to +150
1.5
50
145
Unit
V
°C
°C
W
mA
°C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
θ
ja
where T
a
is the ambient tempera-
ture, P is average operating power and
θ
ja
the thermal resistance of the package. For
this product, use the following
θ
ja
values:
SOJ: 59
o
C/W
TSOP: 87
o
C/W
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Industrial
Commercial
Description
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
Min.
3.0
0
–40
0
Typ.
3.3
0
25
25
Max.
3.6
0
85
70
Unit
V
V
°C
°C
11
12
3
Rev. 1.3 - 4/13/98
PRELIMINARY
PDM31548
DC Electrical Characteristics
(V
CC
= 3.3V
±
0.3V)
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
Test Conditions
V
CC
= Max., V
IN
= Vss to V
CC
V
CC
= Max.,
CE = V
IH
, V
OUT
= Vss to V
CC
Com’l/
Ind.
Com’l/
Ind.
Min.
–5
–5
–0.3
(1)
2.2
—
2.4
Max.
5
5
0.8
Vcc +
0.3
0.4
—
Unit
µA
µA
V
V
V
V
NOTE: 1.V
IL
(min) = –3.0V for pulse width less than 20 ns.
Power Supply Characteristics
-10
Symbol Parameter
I
CC
Operating Current
CE = V
IL
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
≥
V
HC
f=0
V
CC
= Max.,
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
8
8
8
8
8
8
8
mA
20
20
20
20
20
20
20
mA
-12
Ind.
175
-15
-20
Unit
mA
Com’l Com’l
175
165
Com’l Ind. Com’l Ind.
165
185
170
195
NOTES: All values are maximum guaranteed values.
V
LC
≤
0.2V, V
HC
≥
V
CC
– 0.2V
4
Rev. 1.3 - 4/13/98
PRELIMINARY
PDM31548
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
2.5 NS
1.5V
1.5V
See Figures 1 and 2
1
2
3
4
+3.3V
317Ω
D
OUT
351Ω
30 pF
+3.3V
317Ω
D
OUT
351Ω
5 pF
5
6
7
8
9
10
11
12
Figure 1. Output Load
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
)
Rev. 1.3 - 4/13/98
5
