PDM41256
256K Static RAM
32K x 8-Bit
Features
n
1
2
3
4
5
6
7
Description
The PDM41256 is a high-performance CMOS static
RAM organized as 32,768 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
The PDM41256 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41256 comes in two versions:
the standard power version PDM41256SA and the
low power version PDM41256LA. Both versions are
functionally the same and differ only in their power
consumption.
The PDM41256 is available in a 28-pin plastic TSOP
(I) and a 28-pin 300-mil plastic SOJ.
n
High-speed access times
Com’l: 7, 8, 10, 12 and 15ns
Ind’l: 8, 10, 12 and 15ns
(use 15ns for slower designs)
Low power operation (typical)
- PDM41256SA
Active: 475 mW
Standby: 100 mW
- PDM41256LA
Active: 425mW
Standby: 25 mW
Single +5V (±10%) power supply
TTL-compatible inputs and outputs
Packages
Plastic SOJ (300 mil) - SO
Plastic TSOP (I) - T
n
n
n
Functional Block Diagram
A
0
•
•
•
•
•
A
14
Decoder
Memory
Matrix
Addresses
•
•
•
•
•
•
8
9
10
I/O
0
•
•
I/O
7
• • • • •
Input
Data
Control
Column I/O
•
•
11
12
1
CE
WE
OE
•
Rev. 4.4 - 4/29/98
PDM41256
Pin Configurations
TSOP (I)
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A1
A2
SOJ
Pin Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Name
A14-A0
I/O7-I/O0
OE
WE
CE
V
CC
V
SS
Description
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Input
Power (+5V)
Ground
Truth Table
OE
X
L
X
H
WE
X
H
L
H
CE
H
L
L
L
I/O
Hi-Z
D
OUT
D
IN
Hi-Z
MODE
Standby
Read
Write
Output Disable
NOTE: 1. H = V
IH
, L = V
IL
, X = DON’T CARE
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
T
j
Rating
Terminal Voltage with Respect to Vss
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Maximum Junction Temperature
(2)
Com’l.
–0.5 to +7.0
–55 to +125
–55 to +125
1.0
50
125
Ind.
–0.5 to +7.0
–65 to +135
–65 to +150
1.0
50
145
Unit
V
°C
°C
W
mA
°C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
θ
ja
where T
a
is the ambient tempera-
ture, P is average operating power and
θ
ja
the thermal resistance of the package. For
this product, use the following
θ
ja
values:
SOJ: 78
o
C/W
TSOP: 112
o
C/W
2
Rev. 4.4 - 4/29/98
PDM41256
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Commercial
Industrial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
Min.
4.5
0
0
–40
Typ.
5.0
0
25
25
Max.
5.5
0
70
85
Unit
V
V
°C
°C
1
2
3
Unit
DC Electrical Characteristics
(V
CC
= 5.0V
±
10%)
PDM41256SA
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
=8 mA, V
CC
= Min.
I
OL
= 10 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
Test Conditions
V
CC
= MAX., V
IN
= Vss to V
CC
V
CC
= MAX.,
CE = V
IH
, V
OUT
= Vss to V
CC
Com’l/
Ind.
Com’l/
Ind.
Min.
–5
–5
–0.5
(1)
2.2
—
—
2.4
Max.
5
5
0.8
6.0
0.4
0.5
—
PDM41256LA
Min.
–1
–1
–0.5
(1)
2.2
—
—
2.4
Max.
1
1
0.8
6.0
0.4
0.5
—
µA
µA
V
V
V
V
4
5
6
7
NOTE: 1. V
IL
(min) = –3.0V for pulse width less than 20 ns.
Power Supply Characteristics
-7
Symbol Parameter
I
CC
Operating Current
CE = V
IL
f = f
MAX
= 1/t
RC
V
CC
= Max
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
f = f
MAX
= 1/t
RC
V
CC
= Max
I
SB1
Full Standby Current
CE
≥
V
CC
– 0.2V
f=0
V
CC
= Max
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
-8
-10
Com’l.
190
170
Ind.
200
180
-12
Com’l.
170
150
Ind.
180
160
-15
Com’l.
150
130
Ind.
160
140
Units
mA
mA
8
9
10
11
12
3
Power Com’l. Com’l. Ind.
SA
LA
210
190
200
180
210
190
SA
LA
SA
LA
90
90
20
5
80
80
20
5
80
80
20
5
70
70
20
5
70
70
20
5
60
60
20
5
60
60
20
5
50
50
20
5
50
50
20
5
mA
mA
mA
mA
SHADED AREA = PRELIMINARY DATA
NOTE:All values are maximum guaranteed values.
Rev. 4.4 - 4/29/98
PDM41256
Capacitance
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max.
8
8
Unit
pF
pF
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
3 ns
1.5V
1.5V
See Figures 1 and 2
+5V
480Ω
D
OUT
255Ω
30 pF
+5V
480Ω
D
OUT
255Ω
5 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
,
t
HZOE
)
Delta tAA - nS
5
4
3
2
1
0
0
Typical Delta tAA vs Capacitive Loading
30
60
90
120
Additional Lumped Capacitive Loading (pF)
Figure 3.
4
Rev. 4.4 - 4/29/98
PDM41256
Read Cycle No. 1
(1)
t RC
ADDR
t AA
t OH
DOUT
PREVIOUS DATA VALID
DATA VALID
1
2
3
Read Cycle No. 2
(2)
t
RC
ADDR
4
t
HZCE
t
AA
t
ACE
CE
t
LZCE
OE
5
t
HZOE
t
LZOE
D
OUT
DATA VALID
6
7
t
AOE
AC Electrical Characteristics
Description
READ Cycle
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in low Z
(3, 4, 5)
Chip disable to output in high Z
(3, 4, 5)
Chip enable to power up time
(4)
Chip disable to power down time
(4)
Output enable access time
Output enable to output in low Z
(4, 5)
Output disable to output in high Z
(4, 5)
Sym
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
0
5
0
7
5
0
6
3
5
5
0
8
5
0
6
--7
(6)
--8
(6)
-10
(6)
-12
-15
8
ns
15
15
ns
ns
ns
ns
6
ns
ns
15
8
ns
ns
ns
6
ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
7
7
7
3
5
6
0
10
5
0
6
8
8
8
3
5
6
0
12
6
0
10
10
10
3
5
6
0
12
12
12
3
5
15
9
10
11
12
5
SHADED AREA = PRELIMINARY DATA.
Notes referenced are after Data Retention Table.
Rev. 4.4 - 4/29/98
PCB设计
