PDU1064H
6-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU1064H)
FEATURES
•
•
•
•
•
Digitally programmable in 64 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced & buffered
Fits 48-pin DIP socket
GND
ENB
1
2
48
47
GND
OUT
data
3
®
delay
devices,
inc.
PACKAGES
N/C
N/C
OUT
GND
ENB
N/C
N/C
N/C
GND
ENB
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
ENB
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
N/C
N/C
A2
A1
VEE
A0
N/C
A5
A4
VEE
A3
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VEE
N/C
A0
VEE
GND
7
8
9
42
41
40
A1
A2
GND
PIN DESCRIPTIONS
IN
OUT
A0-A5
ENB
VEE
GND
Signal Input
Signal Output
Address Bits
Output Enable
-5 Volts
Ground
A3
VEE
GND
IN
15
16
17
19
34
33
32
A4
A5
GND
PDU1064H-xxC5 SMD
PDU1064H-xxMC5 Mil SMD
VEE
24
PDU1064H-xx DIP
PDU1064H-xxM Mil DIP
FUNCTIONAL DESCRIPTION
The PDU1064H-series device is a 6-bit digitally programmable delay line. The delay, TD
A
, from the input
pin (IN) to the output pin (OUT) depends on the address code (A5-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device, and TD
0
is the inherent delay of
the device. The incremental delay is specified by the dash number of the device and can range from
0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this
signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain
asserted during normal operation.
SERIES SPECIFICATIONS
•
•
•
•
•
•
•
Total programmed delay tolerance:
5% or 2ns,
whichever is greater
Inherent delay (TD
0
):
12ns typical
Setup time and propagation delay:
Address to input setup (T
AIS
):
3.6ns
Disable to output delay (T
DISO
):
1.7ns typical
Operating temperature:
0° to 70° C
Temperature coefficient:
100PPM/°C (excludes TD
0
)
Supply voltage V
EE
:
-5VDC
±
5%
Power Dissipation:
925mw typical (no load)
Minimum pulse width:
20% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU1064H-.5
PDU1064H-1
PDU1064H-2
PDU1064H-3
PDU1064H-4
PDU1064H-5
PDU1064H-6
PDU1064H-8
PDU1064H-10
Incremental Delay
Per Step (ns)
0.5
±
0.3
1.0
±
0.5
2.0
±
0.5
3.0
±
1.0
4.0
±
1.0
5.0
±
1.0
6.0
±
1.0
8.0
±
1.0
10.0
±
1.5
Total
Delay (ns)
31.5
±
2.0
63
±
3.1
126
±
6.3
189
±
9.4
252
±
12.6
315
±
15.7
378
±
18.9
504
±
25.2
630
±
31.5
NOTE: Any dash number between .5 and 10
not shown is also available.
©
1997 Data Delay Devices
Doc #97046
12/17/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU1064H
APPLICATION NOTES
ADDRESS UPDATE
The PDU1064H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
T
OAX
, is required before the address lines can
change. This time is given by the following
relation:
T
OAX
= max { (A
i
- A
i-1
) * T
INC
, 0 }
where A
i-1
and A
i
are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T
OAX
has elapsed.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
T
DISH
= A
i
* T
INC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
possibility of spurious signals persists until the
required T
DISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the
AC
Characteristics
table. The
recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The
suggested
conditions are
those for which signals will propagate through the
unit without significant distortion. The
absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
A5-A0
T
AENS
ENB
T
ENIS
IN
TD
A
OUT
A
i-1
T
OAX
T
AIS
A
i
PW
IN
T
DISH
PW
OUT
T
DISO
Figure 1: Timing Diagram
Doc #97046
12/17/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
PDU1064H
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
Absolute
Input Period
Suggested
Recommended
Absolute
Input Pulse Width
Suggested
Recommended
SYMBOL
TD
T
TD
0
T
DISO
T
AENS
T
AIS
T
ENIS
T
OAX
T
DISH
PER
IN
PER
IN
PER
IN
PW
IN
PW
IN
PW
IN
MIN
TYP
63
12.0
1.7
UNITS
T
INC
ns
ns
ns
ns
ns
1.0
3.6
3.6
See Text
See Text
16
40
200
8
20
100
% of TD
T
% of TD
T
% of TD
T
% of TD
T
% of TD
T
% of TD
T
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
V
EE
V
IN
T
STRG
T
LEAD
MIN
-7.0
V
EE
- 0.3
-55
MAX
0.3
0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 75C)
PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
SYMBOL
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
MIN
-1.020
-1.950
-1.480
475
0.5
TYP
MAX
-0.735
-1.600
-1.070
UNITS
V
V
V
V
µA
µA
NOTES
V
IH
= MAX,50Ω to -2V
V
IL
= MIN, 50Ω to -2V
V
IH
= MAX
V
IL
= MIN
Doc #97046
12/17/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
PDU1064H
PACKAGE DIMENSIONS
48 47
42 41 40
34 33 32
.400
TYP.
1 2
7
8
9
15 16 17
19
24
2.450 TYP.
.020 .320
TYP. MAX.
.150
±.030
.100
.600
.700
.800
1.400
1.500
1.600
1.800
.075
2.300
.018
TYP.
.012 TYP.
.300
TYP.
PDU1064H-xx (Commercial DIP)
PDU1064H-xxM (Military DIP)
.020 TYP.
.040 TYP.
.010±.002
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
.710 .590
±.005
MAX.
.882
±.005
.007
±.005
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
.090
1.100
2.080±.020
.100
.280
MAX.
.050
±.010
PDU1064H-xxC5 (Commercial SMD)
PDU1064H-xxMC5 (Military SMD)
Doc #97046
12/17/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
PDU1064H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
-5.0V
±
0.1V
Input Pulse:
Standard 10KH ECL
levels
Source Impedance:
50Ω Max.
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
PW
IN
= 1.5 x Total Delay
Period:
PER
IN
= 10 x Total Delay
OUTPUT:
Load:
C
load
:
Threshold:
50Ω to -2V
5pf
±
10%
(V
OH
+ V
OL
) / 2
(Rising & Falling)
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
REF
PULSE
GENERATOR
OUT
TRIG
IN
DEVICE UNDER
TEST (DUT)
OUT
IN
TRIG
OSCILLOSCOPE
ADDRESS SELECT
Test Setup
PER
IN
PW
IN
T
RISE
INPUT
SIGNAL
80%
50%
20%
T
FALL
V
IH
80%
50%
20%
V
IL
T
FALL
T
RISE
OUTPUT
SIGNAL
V
OH
50%
50%
V
OL
Timing Diagram For Testing
Doc #97046
12/17/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
嵌入式系统
