PDU15F
5-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU15F)
FEATURES
•
•
•
•
•
•
•
•
Digitally programmable in 32 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
Input & outputs fully TTL interfaced & buffered
10 T
2
L fan-out capability
Fits standard 24-pin DIP socket
Auto-insertable
OUT/
OUT
EN/
GND
N/C
IN
N/C
GND
N/C
N/C
EN/
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
data
3
®
delay
devices,
inc.
PACKAGES
VCC
A0
A1
A2
VCC
N/C
N/C
N/C
VCC
A3
A4
N/C
PDU15F-xx
DIP
PDU15F-xxA4
Gull-Wing
PDU15F-xxB4
J-Lead
PDU15F-xxM
Military DIP
PDU15F-xxMC4
Military Gull-Wing
FUNCTIONAL DESCRIPTION
The PDU15F-series device is a 5-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A4-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
PIN DESCRIPTIONS
IN
OUT
OUT/
A0-A4
EN/
VCC
GND
Delay Line Input
Non-inverted Output
Inverted Output
Address Bits
Output Enable
+5 Volts
Ground
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
•
•
•
•
•
•
•
•
Total programmed delay tolerance:
5% or 1ns,
whichever is greater
Inherent delay (TD
0
):
9ns typical (OUT)
8ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (T
AIS
):
5ns
Disable to output delay (T
DISO
):
6ns typ. (OUT)
Operating temperature:
0° to 70° C
Temperature coefficient:
100PPM/°C (excludes TD
0
)
Supply voltage V
CC
:
5VDC
±
5%
Supply current:
I
CCH
= 74ma
I
CCL
= 30ma
Minimum pulse width:
10% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU15F-.5
PDU15F-1
PDU15F-2
PDU15F-3
PDU15F-4
PDU15F-5
PDU15F-6
PDU15F-8
PDU15F-10
PDU15F-12
PDU15F-15
PDU15F-20
Incremental Delay
Per Step (ns)
.5
±
.3
1
±
.5
2
±
.5
3
±
1.0
4
±
1.0
5
±
1.0
6
±
1.0
8
±
1.0
10
±
1.5
12
±
1.5
15
±
1.5
20
±
2.0
Total Delay
Change (ns)
15.5
±
1.0
31
±
1.6
62
±
3.1
93
±
4.7
124
±
6.2
155
±
7.8
186
±
9.3
248
±
12.4
310
±
15.5
372
±
18.6
465
±
23.3
620
±
31.0
©
1997 Data Delay Devices
NOTE: Any dash number between .5 and 20 not
shown is also available.
Doc #97003
1/13/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU15F
APPLICATION NOTES
ADDRESS UPDATE
The PDU15F is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
T
OAX
, is required before the address lines can
change. This time is given by the following
relation:
T
OAX
= max { (A
i
- A
i-1
) * T
INC
, 0 }
where A
i-1
and A
i
are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T
OAX
has elapsed.
A similar situation occurs when using the EN/
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the EN/ signal high and
the IN signal low for a time given by:
T
DISH
= A
i
* T
INC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
possibility of spurious signals persists until the
required T
DISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the
AC
Characteristics
table. The
recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The
suggested
conditions are
those for which signals will propagate through the
unit without significant distortion. The
absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
A4-A0
T
AENS
EN/
T
ENIS
IN
TD
A
OUT
A
i-1
T
OAX
T
AIS
A
i
PW
IN
T
DISH
PW
OUT
T
DISO
T
SKEW
OUT/
Figure 1: Timing Diagram
Doc #97003
1/13/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
PDU15F
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
Output Skew
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
Absolute
Input Period
Suggested
Recommended
Absolute
Input Pulse Width
Suggested
Recommended
SYMBOL
TD
T
TD
0
T
SKEW
T
DISO
T
AENS
T
AIS
T
ENIS
T
OAX
T
DISH
PER
IN
PER
IN
PER
IN
PW
IN
PW
IN
PW
IN
MIN
TYP
31
9.0
1.5
6.0
UNITS
T
INC
ns
ns
ns
ns
ns
ns
2.0
5.0
2.5
See Text
See Text
20
40
200
10
20
100
% of TD
T
% of TD
T
% of TD
T
% of TD
T
% of TD
T
% of TD
T
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
V
CC
V
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-55
MAX
7.0
V
DD
+0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current at Maximum
Input Voltage
High Level Input Current
Low Level Input Current
Short-circuit Output Current
Output High Fan-out
Output Low Fan-out
SYMBOL
V
OH
V
OL
I
OH
I
OL
V
IH
V
IL
V
IK
I
IHH
I
IH
I
IL
I
OS
MIN
2.5
TYP
3.4
0.35
MAX
UNITS
V
V
mA
mA
V
V
V
mA
µA
mA
mA
Unit
Load
NOTES
V
CC
= MIN, I
OH
= MAX
V
IH
= MIN, V
IL
= MAX
V
CC
= MIN, I
OL
= MAX
V
IH
= MIN, V
IL
= MAX
0.5
-1.0
20.0
2.0
0.8
-1.2
0.1
20
-0.6
-150
25
12.5
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
-60
Doc #97003
1/13/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
PDU15F
PACKAGE DIMENSIONS
.020 TYP.
.040 TYP.
.010 TYP.
24 23 22 21 20 19 18 17 16 15 14 13
.270
TYP.
24 23 22 21 20 19 18 17 16 15 14 13
1
2
3
4
5
6
7
8
9
10 11 12
.430
TYP.
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
.110
1.100
1.290 MAX.
.100
.300
MAX.
.050
TYP.
1
2
3
4
5
6
7
8
9 10 11 12
1.270
.280
MAX.
.290
MAX.
Commercial Gull-Wing (PDU15F-xxA4)
.020 TYP.
.040 TYP.
.050 TYP.
.320
TYP.
24 23 22 21 20 19 18 17 16 15 14 13
.270
TYP.
.015 TYP.
.018 TYP.
.070 MAX.
1.100
1
2
3
4
5
6
7
8
9
10 11 12
.010±.002
.110
.350
MAX.
1.100
1.290 MAX.
.100
.350
MAX.
.110
TYP.
Commercial DIP (PDU15F-xx)
Commercial J-Lead (PDU15F-xxB4)
24 23 22 21 20
16 15 14
.410
MAX.
1
2
3
4
6
8
11 12
.020 TYP.
.040 TYP.
.010±.002
1.300 TYP.
24 23 22 21 20 19 18 17 16 15 14 13
.300
MAX.
.130
MIN.
.018 TYP.
1.100 TYP.
.100 TYP.
.100
1
2
3
4
5
6
7
8
9
10 11 12
.710 .590
±.005
MAX.
.882
±.005
.007
±.005
.012 TYP.
.090
.300
TYP.
1.100
1.280±.020
.100
.280
MAX.
.050
±.010
Military DIP (PDU15F-xxM)
Military Gull-Wing (PDU15F-xxMC4)
Doc #97003
1/13/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
PDU15F
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
5.0V
±
0.1V
Input Pulse:
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PW
IN
= 1.5 x Total Delay
Period:
PER
IN
= 4.5 x Total Delay
OUTPUT:
Load:
C
load
:
Threshold:
1 FAST-TTL Gate
5pf
±
10%
1.5V (Rising & Falling)
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
REF
PULSE
GENERATOR
OUT
TRIG
IN
DEVICE UNDER
TEST (DUT)
OUT
IN
TRIG
TIME INTERVAL
COUNTER
Test Setup
PER
IN
PW
IN
T
RISE
INPUT
SIGNAL
2.4V
1.5V
0.6V
T
FALL
V
IH
2.4V
1.5V
0.6V
V
IL
TD
AF
TD
AR
OUTPUT
SIGNAL
V
OH
1.5V
1.5V
V
OL
Timing Diagram For Testing
Doc #97003
1/13/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
