Advance Information
PE97632
Product Description
Peregrine’s PE97632 is a high performance fractional-N PLL
capable of frequency synthesis up to 3.2 GHz. The device is
designed for superior phase noise performance while providing
an order of magnitude reduction in current consumption, when
compared with the existing commercial space PLLs.
The PE97632 features a 10/11 dual modulus prescaler,
counters, a delta sigma modulator, and a phase comparator as
shown in Figure 1. Counter values are programmable through
either a serial interface or directly hard-wired.
The PE97632 is optimized for commercial space applications.
Single Event Latch up (SEL) is physically impossible and
Single Event Upset (SEU) is better than 10-9 errors per bit /
day. Fabricated in Peregrine’s patented UTSi® (Ultra Thin
Silicon) CMOS technology, the PE97632 offers excellent RF
performance and intrinsic radiation tolerance.
3.2 GHz Delta-Sigma modulated
Fractional-N Frequency Synthesizer
for Low Phase Noise Applications
Features
•
3.2 GHz operation
•
÷10/11 dual modulus prescaler
•
Phase detector output
•
Serial or Direct mode access
•
Frequency selectivity: Comparison
frequency / 2
18
•
Low power — 50 mA at 3.3 V
•
Rad-Hard
•
Ultra-low phase noise
•
68-lead CQFJ
Figure 1. Block Diagram
F
in
F
in
M
8:0
A
3:0
R
5:0
Pre_en
Sdata
Primary
21-bit
Latch
Prescaler
10/11
Main
Counter
13
20
Secon-
dary
20-bit
Latch
Auxilia-
ry
20-bit
Latch
+
13
20
18
DSM
19
4
6
6
PD_U
Phase
Detector
PD_D
f
r
18
K
17:0
Direct
R Counter
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Page 1 of 16
PE97632
Advance Information
Figure 2. Pin Configuration and package photo
RAND_EN
MS2_SEL
GND
GND
61
ENH
V
DD
V
DD
63
NC
F
R
62
R
5
R
4
R
3
R
2
R
1
R
0
K
1
K
0
68
67
65
66
64
9
7
6
4
2
8
5
3
1
V
DD
10
K
2
11
K
3
12
K
4
13
K
5
14
K
6
15
K
7
16
K
8
17
K
9
18
K
10
19
K
11
20
K
12
21
K
13
22
K
14
23
K
15
24
K
16
25
K
17
26
27
V
DD
28
GND
29
M
0
30
M
1
31
M
2
32
M
3
33
M
4
34
M
5
35
M
6
36
M
7
37
M
8
38
A
0
39
A
1
40
A
2
41
A
3
42
DIRECT
43
PRE_EN
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
DD
V
DD
GND
PD_U
NC
PD_D
GND
V
DD
D
OUT
LD
C
EXT
GND
FIN
FIN
V
DD
GND
V
DD
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin
Name
R
0
R
1
R
2
R
3
R
4
R
5
K
0
K
1
GND
V
DD
K
2
K
3
K
4
K
5
K
6
Valid
Mode
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Type
Input
Input
Input
Input
Input
Input
Input
Input
Downbond
(Note 1)
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
R Counter bit4.
R Counter bit5 (MSB).
K Counter bit0 (LSB).
K Counter bit1.
Ground
Digital core V
DD
.
K Counter bit2.
K Counter bit3.
K Counter bit4.
K Counter bit5.
K Counter bit6.
Description
Direct
Direct
Direct
Direct
Direct
Input
Input
Input
Input
Input
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 16
Document No. 70-0205-02
│
UltraCMOS™ RFIC Solutions
PE97632
Advance Information
Pin No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin
Name
K
7
K
8
K
9
K
10
K
11
K
12
K
13
K
14
K
15
K
16
K
17
V
DD
GND
M
0
M
1
M
2
M
3
M
4
Valid
Mode
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Downbond
K Counter bit7.
K Counter bit8.
K Counter bit9.
K Counter bit10.
K Counter bit11.
K Counter bit12.
K Counter bit13.
K Counter bit14.
K Counter bit15.
K Counter bit16.
K Counter bit17 (MSB).
Digital core V
DD
.
Ground
M Counter bit0 (LSB).
M Counter bit1.
M Counter bit2
M Counter bit3.
M Counter bit4.
Description
Direct
Direct
Direct
Direct
Direct
Serial
Direct
Serial
Direct
Serial
Direct
Direct
Direct
Direct
Serial
Direct
Direct
Both
Direct
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Downbond
33
S_WR
M
5
34
SDATA
M
6
35
SCLK
36
37
38
M
7
M
8
A
0
A
1
39
E_WR
40
41
42
43
44
45
A
2
A
3
DIRECT
Pre_en
V
DD
GND
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register
data are transferred to the secondary register on S_WR or Hop_WR rising edge.
M Counter bit5.
Binary serial data input. Input data entered MSB first.
M Counter bit6.
Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR “low”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
M Counter bit7.
M Counter bit8 (MSB).
A Counter bit0 (LSB).
A Counter bit1.
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into
the enhancement register on the rising edge of Sclk.
A Counter bit2.
A Counter bit3 (MSB).
Direct mode select. “High” enables direct mode. “Low” enables serial mode.
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Digital core V
DD
.
Ground
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PE97632
Advance Information
Pin No.
46
47
48
49
50
Pin
Name
V
DD
F
in
F
in
GND
CEXT
Valid
Mode
Type
(Note 1)
Prescaler V
DD
.
Description
Both
Both
Input
Input
Downbond
Output
Prescaler input from the VCO. 3.2 GHz max frequency.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50
Ω
resistor directly to the ground plane.
Ground
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Data out function, enabled in enhancement mode.
Output driver/V
DD
.
Ground
PD_D pulses down when f
p
leads f
c
. PD_U is driven to GND when CPSEL = “High”.
No Connect
Both
Both
Both
51
52
53
54
55
56
57
58
59
60
61
62
63
64
LD
D
OUT
V
DD
GND
PD_D
NC
PD_U
GND
V
DD
V
DD
GND
f
r
V
DD
V
DD
GND
Output
Output
(Note 1)
Downbond
Both
Both
Both
Output
Output
Downbond
(Note 1)
(Note 1)
Downbond
PD_U pulses down when f
c
leads f
p
. PD_D is driven to GND when CPSEL = “High”.
Ground
Output driver/V
DD
.
Phase detector V
DD
.
Ground
Reference frequency input.
Reference V
DD
.
Digital core V
DD
.
Ground
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
No Connect
Both
Input
(Note 1)
(Note 1)
Downbond
65
66
67
68
Note 1:
Note 2:
ENH
NC
MS2_SEL
RND_SEL
Both
Both
Both
Input
Input
Input
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 2
19
.
Both
All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
All digital input pins have 70 kΩ pull-down resistors to ground.
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 16
Document No. 70-0205-02
│
UltraCMOS™ RFIC Solutions
PE97632
Advance Information
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Electrostatic Discharge (ESD) Precautions
Units
V
V
mA
mA
°C
4.0
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature range
Min
-0.3
-0.3
-10
-10
-65
Max
V
DD
+
0.3
+10
+10
150
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.45
85
Units
V
°C
Table 4. ESD Ratings
Symbol
V
ESD
Parameter/Conditions
ESD voltage human body model
(Note 1)
Level
1000
Units
V
Note 1:
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
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©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 16
模拟与混合信号
