PEX8603, PCI Express Gen 2 Switch, 3 Lanes, 3 Ports
Highlights
PEX8603 General Features
o
3-lane, 3-port PCIe Gen2 switch
Integrate 5.0 GT/s SerDes
o
10 x 10mm
2
, 136-pin QFN
package
o
Typical Power: 0.7 Watts
The ExpressLane
™
PEX8603 device offers PCI Express switching capability
enabling users to add scalable high bandwidth non-blocking interconnection
to a wide variety of applications including control plane applications,
consumer applications and embedded systems. The PEX8603 is well suited
for fan-out and peer-to-peer applications.
Low Packet Latency & High Performance
The PEX8603 architecture supports packet cut-thru with a maximum latency of
250ns in x1 to x1 configuration. This, combined with low power consumption
and non-blocking internal switch architecture, provides full line rate on all ports
for low-power applications such as consumer and embedded. The low latency
enables applications to achieve high throughput and performance. In addition to
low latency, the device supports a max payload size of 256 bytes.
Data Integrity
The PEX8603 provides end-to-end CRC protection (ECRC) and Poison bit
support to enable designs that require guaranteed error-free packets. PLX also
supports data path parity and memory (RAM) error correction as packets pass
through the switch.
Power Management and Reference Clock Buffers
The PEX8603 supports the following power management states: L0, L0s, L1,
L2/L3 Ready, L2 and L3. Moreover, the PEX8603 supports Vaux along with the
external signal WAKE# and the in-band Beacon for the PCIe endpoints to use to
inform the system host to exit the low power savings mode.
The PEX 8603 supports two pairs of buffered, 100 MHz HCSL output clocks,
one pair for each downstream port of the switch. Each clock output pair can be
disabled by software or serial EEPROM when not in use, for additional power
savings. This feature greatly reduces system BOM cost by eliminating the need
for extra clock buffers on the PCB.
Interoperability
The PEX8603 is designed to be fully compliant with the PCI Express Base
Specification r2.1 and is backwards compatible to PCI Express Base
Specification r1.1 and r1.0a. Additionally each port supports auto-negotiation and
polarity reversal. Furthermore, the PEX8603 is designed for Microsoft Windows
7 compliance. All PLX switches undergo thorough interoperability testing in
PLX’s Interoperability Lab and compliance testing at the PCI-SIG plug-fest to
ensure compatibility with PCI Express devices in the market.
Device Operation Configuration Flexibility
The PEX8603 provides several ways to configure its operations. The device can
be configured through strapping pins, I2C interface, CPU configuration cycles
and/or an optional serial EEPROM. This allows for easy debug during the
development phase and functional monitoring during the operation phase.
PEX8603 Key Features
o
Standards Compliant
PCI Express Base Specification, r2.1
(backwards compatible w/ PCIe
1.0a/1.1)
PCI Power Management Spec, r1.2
Microsoft Windows 7 Compliant
Dynamic SerDes speed control
o
High Performance
Non-blocking switch fabric
Full line rate on all ports
Packet Cut-Thru with 250ns max
packet latency (x1 to x1)
256B Max Payload Size
o
Flexible Configuration
Ports configurable as x1, x2
Registers configurable with strapping
pins, EEPROM, I
2
C, or host software
Reference Clock Buffered Output
signals for downstream ports
Lane and polarity reversal
Compatible with PCIe 1.0a PM
o
Quality of Service (QoS)
Eight traffic classes per port
Round-robin source port arbitration
Relaxed PCI Ordering
o
Reliability, Availability,
Serviceability
visionPAK™
•
Per Port Performance Monitoring
•
Per port payload & header counters
•
SerDes Eye Capture
•
Error Injection and Loopback
All ports hot plug capable thru I
2
C
(Hot-Plug Controller on every port)
Data Path parity
Memory (RAM) Error Correction
signals
INTA# and FATAL_ERR#
Advanced Error Reporting
Port Status bits and GPIO available
Per port error diagnostics
JTAG AC/DC boundary scan
o
Power Management
WAKE#, Beacon, Vaux support
© PLX Technology, www.plxtech.com
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PEX8603, PCI Express Gen 2 Switch, 3 Lanes, 3 Ports
Flexible Port Configurations
The PEX8603 flexible architecture supports a number of port
configurations as required by the target applications as shown in
figure 1 below.
x2
x1
With WAKE#/Beacon support integrated in the switch, the
PEX8603 is well suited for low power consumer applications
such as that described in Figure 2 of a dual-band wireless
adapter.
Modem Set-top Box
With its small footprint, the PEX8603 is ideal for consumer
applications. Figure 3 shows a high level diagram for a modem
set-top box. The PEX8603 provides connectivity to a WiFi
controller for immediate use as well as future expansion.
PEX 8603
PEX 8603
x1
x1
x1
Figure 1. Port Configurations
SerDes Power and Signal Management
The PEX8603 provides low power capability that is fully
compliant with the PCI Express power management
specification. In addition, the SerDes physical links can be
turned off when unused for even lower power. The PEX8603
supports
software control
of the
SerDes outputs
to allow
optimization of power and signal strength in a system. The PLX
SerDes implementation supports four levels of power – off, low,
typical, and high. The SerDes block also supports
loop-back
modes
and
advanced reporting of error conditions,
which
enables efficient debug and management of the entire system.
Figure 3. Modem Set-top Box Block Diagram
Fan-Out
The PEX8603 can be used in as a fan-out switch to provide
additional x1ports. The PEX8603 SerDes can function at
2.5GT/s or 5
Port Arbitration and QoS
The PEX8603 switch supports hardware fixed Round-Robin
Ingress Port Arbitration. The PEX8603 also supports Eight
Traffic Classes (TCs) as defined in the PCIe specification.
Applications
Suitable for
fan-out, consumer, control plane applications,
and embedded systems,
PEX8603 is suited for a wide variety
of form factors and applications.
PCH
x1
CPU
..
x1
Gen1
Dual-Band Wireless Adapter
The PEX8603 switch, with its small package and low power can
be used in consumer applications such as a dual-band wireless
adapter.
PEX 8603
x1
2.5GT/s; 5.0GT/s
Figure 4. Fan-out
Bandwidth Bridge
There are three PCIe lanes available in the PEX8603. Each one
can represent an individual port or alternatively two can be
joined to form a x2 port. A x2 port can provide double the
bandwidth of a x1 port when all lanes are operating at the same
data rates (all at 2.5GT/s or 5.0GT/s). In some instances, the
need to match the bandwidth between devices running at
different data rates (2.5GT/s vs 5.0GT/s) is required to sustain
the performance of the faster device. Figure 5 provides an
Figure 2. Dual-band Wireless Adapter
© PLX Technology, www.plxtech.com
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PEX 8603, PCI Express Gen 2 Switch, 3 Lanes, 3 Ports
example where the PEX8603 is configured as x2, x1. In this
example, the x2 link is running at the lower data rate (2.5GT/s)
while a single x1 port is running at the higher data rate (5.0
GT/s). In this usage model, the PEX8603 acts as a bridge
between Gen 1 and Gen 2 devices allowing the faster device to
operate at its full bandwidth capabilities.
ExpressLane PEX8603 RDK
The PEX8603 RDK is a hardware module containing the
PEX8603 which plugs right into your system. The PEX8603
RDK can be used to test and validate customer software, or used
as an evaluation vehicle for PEX8603 features and benefits. The
PEX8603 RDK provides everything that a user needs to get their
hardware and software development started.
PORT 1 - X4
Lane Status
LEDs
PORT 2 - X4
Manual
Reset
JTAG
Header
DIP switch
for cfg.
12V-to-1V
Non-Iso
Converter
PEX 8603
8518
RefClk
Reset
Ckt.
(Upstream Port)
x4
PEX8518
PEX
I2C
EEPROM
PERST#
Figure 6. PEX8603 Rapid Development Kit
Figure 5. Gen 1 to Gen 2 Bandwidth Bridge
Software Development Kit (SDK)
PLX’s Software Development Kit is available for download at
www.plxtech.com/sdk.
The software development kit includes
drivers, source code, and GUI interfaces to aid in configuring
and debugging the PEX8603.
Both
performancePAK
and
visionPAK
are supported by PLX’s
RDK and SDK, the industry’s most advanced hardware- and
software-development kits.
Software Usage Model
From a system model viewpoint, each PCI Express port is a
virtual PCI to PCI bridge device and has its own set of PCI
Express configuration registers. It is through the upstream port
that the BIOS or host can configure the other ports using
standard PCI enumeration. The virtual PCI-to-PCI bridges
within the PEX8603 are compliant to the PCI and PCI Express
system models. The Configuration Space Registers (CSRs) in a
virtual primary/secondary PCI-to-PCI bridge are accessible by
type 0 configuration cycles through the virtual primary bus
interface (matching bus number, device number, and function
number).
Product Ordering Information
Part Number
PEX8603-AA50NI G
PEX8603-AA RDK
Description
3 Lane, 3 Port PCI Express Gen 2.0
Switch, Pb-Free (10x10mm
2
aQFN)
PEX 8603 Rapid Development Kit +
CM108 (one x1 upstream port, two x1
downstream ports)
PEX 8603 Rapid Development Kit +
CM107 (one x2 upstream port, one x1
downstream port)
Interrupt Sources/Events
The PEX8603 supports the INTx interrupt message type
(compatible with PCI 2.3 Interrupt signals) or Message Signaled
Interrupts (MSI) when enabled. Interrupts/messages are
generated by PEX8603 for Hot-Plug events, doorbell interrupts,
baseline error reporting, and advanced error reporting.
PEX 8603-AA-2U1D
RDK
Development Tools
PLX offers hardware and software tools to enable rapid
customer design activity. These tools consist of a hardware
module (PEX8603 RDK), hardware documentation
(available at
www.plxtech.com),
and a Software Development
Kit (also available at
www.plxtech.com).
PLX Technology, Inc. All rights reserved. PLX, the PLX logo, ExpressLane,
Read Pacing, Dual Cast, performancePAK and visionPAK are trademarks of
PLX Technology, Inc. All other product names that appear in this material are
for identification purposes only and are acknowledged to be trademarks or
registered trademarks of their respective companies. Information supplied by
PLX is believed to be accurate and reliable, but PLX assumes no responsibility
for any errors that may appear in this material. PLX reserves the right, without
notice, to make changes in product design or specification.
Visit
www.plxtech.com
for more information.
© PLX Technology, www.plxtech.com
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