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PROGRAMMABLE LOGIC DELAY LINES
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PFLDL-TTL-5-XXX
3-Bit Programmable FAST TTL Delay Line
- T²L compatible input and output
- Delays stable and precise
- 14-pin DIP package
- Leads -- thru-hole, J, Gull Wing or Tucked
- Available in delays up to 355ns
- Available in 23 delay steps with resolution from .5 to 50ns
- Propagation delays fully compensated
- All delays digitally programmable
- 10 T²L fan-out capacity
Made in U.S.A.
DESIGN NOTES
The "DIP Series" of Programmable Logic Delay Lines developed by Engineered
Components Company have been designed to allow for final delay adjustment during or
after installation in a circuit. These Logic Delay Lines incorporate required driving and
pick-off circuitry and are contained in a 14-pin DIP package compatible with FAST and
Schottky T²L circuits. These modules are of hybrid construction utilizing the proven
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technologies of active integrated circuitry and of passive networks utilizing capacitive,
inductive and resistive elements. The MTBF on these modules, when calculated per MIL-
HDBK-217 for a 50°C ground fixed environment, is in excess of 2.5 million hours. The
design includes compensation for propagation delays and incorporates internal
termination at the output. No additional external components are needed to obtain the
required delay.
The Logic Delay Lines are digitally programmable by the presence of either a "1" or a "0"
at each of the programming pins. Since the input and output terminals are fixed and the
programming is accomplished only by DC voltage levels, programming may be
accomplished by remote switching or permanent termination of the appropriate
programming pins to logic "1" or "0" levels; the Logic Delay Line may also be
programmed automatically by computer generated data. MUX set-up time is 4ns typical.
When no need exists in the application to change delay time during normal use, the
desired delay is most conveniently established by use of a ground pad around each
programming pin; programming is accomplished by cutting off those pins which are to
remain at state "1" before insertion of the Logic Delay Line into the printed circuit board.
The PFLDL-TTL is offered in 23 models with time delays to a maximum of 355ns and
with step resolution as shown in the Part Number Table. Programming of maximum
delay is accomplished in 8 steps in accordance with the Truth Table examples.
Tolerances on minimum delay, delay change per step and deviation from the
programmed delay are shown in the Part Number Table.
Delay time is measured at the +1.5V level on the leading edge. Rise time for all modules
is 4ns maximum, when measured from 0.8V to 2.0V. Temperature coefficient of delay is
approximately -500 ppm/°C over the operating temperature range of 0 to +70°C.
The PFLDL-TTL is designed for use with positive input pulses and will reproduce these at
the output without inversion. A complementary (OUT) output is provided approximately in
1ns after normal output. All modules can be driven by a standard Schottky T²L gate.
Output is FAST T²L toggle; programming in puts are FAST T²L single fan-in. These Logic
Delay Lines have the capability of driving up to 10 T²L loads.
These "DIP Series" Programmable Logic Delay Lines are packaged in a 14-pin DIP
housing, molded of flame-proof Diallyl Phthalate per ASTM D 5948, type SDG-F, and are
fully encapsulated in epoxy resin. Thru-hole, J, Gull Wing or Tucked Lead configurations
area available on these modules (see Part Number Table note to specify). Leads meet
the solderability requirements of MIL-STD-202, Method 208. Corner standoffs on the
housing of the thru-hole lead version and lead design of the surface mount versions
provide positive standoff from the printed circuit board to permit solder-fillet formation and
flush cleaning of solder-flux residues for improved reliability.
Marking consists of manufacturer's name, logo (EC²), part number, terminal identification
and date code of manufacture. All marking is applied by silk screen process using white
epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification
required by MIL-STD-202, Method 215.
TEST CONDITIONS
1. All measurements are made at 25°C.
2. Vcc supply voltage is maintained at 5.0V DC.
3. All units are tested using a Schottky toggle-type positive input pulse and one ACT
load at the output.
4. Input pulse width used is 600ns. Pulse period for all units is 5,000ns.
OPERATING SPECIFICATIONS
*Vcc supply voltage: ........... 4.75 to 5.25V DC
Vcc supply current: ............ 40mA typical
Logic 1 input:
Voltage .................... 2V min.; 5.5 max.
Current .................... 2.7V = 40uA max.
5.5V = 2mA max.
Logic 0 input:
Voltage .................... 0.8V max.
Current .................... -1.2mA max
Logic 1 Voltage out: ........... 2.7V min.
Logic 0 Voltage out: ........... 0.5 max.
Operating temperature range: ... 0 to +70°C.
Storage temperature: ........... -55 to +125°C.
* Delays increase approximately 2% for an increase or decrease of 5% in supply
voltage.
PART NUMBER TABLE
ø DELAYS AND TOLERANCES (in ns)
*Step Zero
Delay Time
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
Maximum Delay Delay Change
Time (Nom)
Per Step
8.5
12
19
26
33
40
47
54
61
68
75
82
89
96
103
110
145
180
215
250
285
320
355
.5 ±.3
1 ±.3
2 ±.4
3 ±.5
4 ±.5
5 ±.5
6 ±.6
7 ±.7
8 ±.8
9 ±.9
10 ±1.0
11 ±1.1
12 ±1.2
13 ±1.3
14 ±1.4
15 ±1.5
20 ±2.0
25 ±2.5
30 ±3.0
35 ±3.5
40 ±4.0
45 ±4.5
50 ±5.0
**Maximum
Dev iation From
Programmed Delay
±.4
±.4
±.6
±.8
±.9
±1.0
±1.2
±1.4
±1.6
±1.8
±2.0
±2.2
±2.4
±2.6
±2.8
±3.0
±4.0
±5.0
±6.0
±7.0
±5.0
±9.0
±10.0
Part Number
PFLDL-TTL-5-.5
PFLDL-TTL-5-1
PFLDL-TTL-5-2
PFLDL-TTL-5-3
PFLDL-TTL-5-4
PFLDL-TTL-5-5
PFLDL-TTL-5-6
PFLDL-TTL-5-7
PFLDL-TTL-5-8
PFLDL-TTL-5-9
PFLDL-TTL-5-10
PFLDL-TTL-5-11
PFLDL-TTL-5-12
PFLDL-TTL-5-13
PFLDL-TTL-5-14
PFLDL-TTL-5-15
PFLDL-TTL-5-20
PFLDL-TTL-5-25
PFLDL-TTL-5-30
PFLDL-TTL-5-35
PFLDL-TTL-5-40
PFLDL-TTL-5-45
PFLDL-TTL-5-50
TRUTH TABLE EXAMPLES
3 0 0 0 0 1 1 1 1
2 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1
PFLDL-TTL-5-1
PFLDL-TTL-5-2
PFLDL-TTL-5-3
ETC.
5 1 2 3 4 5 6 7
5 2 4 6 8 10 12 14
5 3 6 9 12 15 18 21
*Delay at step zero is referenced to the input pin.
**All delay times after step zero are referenced to step zero.
ø All modules can be operated with a minimum input pulse width of 40% of full delay and
pulse period approaching square wave; since delay accuracies may be somewhat
degraded, it is suggested that the module be evaluated under the intended specific
operating conditions.
Special modules can be readily manufactured to improve accuracies and/or provide
customer specified delay times for specific applications.
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