Space Applications Only
PHR
Vishay Sfernice
ESCC (
) 4001/023 Qualified High Precision (5 ppm, 0.01 %),
Thin Film Chip Resistors
FEATURES
•
Load life stability at ± 70 °C for 2000 h: 0.15 %
under Pn
•
Low temperature coefficient down to ± 5 ppm/°C
•
Very low noise (< 35 dB) and voltage
coefficient (< 0.01 ppm/V)
•
Resistance range: 50
Ω
to 3 MΩ (depending on
size)
•
Laser trimmed tolerances to ± 0.01 %
•
TCR in lot tracking
≤
5 ppm/°C
•
Termination: Thin film technology
•
SnPb terminations over nickel barrier
•
ESCC 4001 (generic spec)
•
ESCC 4001/023 (detailed spec)
•
ESCC qualified
•
SMD wraparound chip resistor
•
Halogen-free according to IEC 61249-2-21
Vishay Sfernice Thin Film division holds ESCC QML
qualification (ESCC technology flow qualification).
These HiRel components are ideal for low noise and
precision applications, superior stability, low temperature
coefficient of resistance, and low voltage coefficient,
VISHAY SFERNICE’s precision thin film wraparound
resistors exceed requirements of MIL-PRF-55342G
characteristics Y (± 10 ppm/°C).
DIMENSIONS
A
D
D
C
B
E
E
CASE SIZE
0603
0805
1206
2010
MIN.
1.39
1.78
2.87
4.95
A
MAX.
2.16
2.55
3.64
5.72
MIN.
0.62
1.14
1.47
2.41
DIMENSIONS in millimeters
B
C
MAX.
MIN.
1.01
0.25
1.53
0.25
1.86
0.25
2.80
0.25
D/E
MAX.
1.02
1.02
1.02
1.02
MIN.
0.25
0.25
0.25
0.35
MAX.
0.51
0.51
0.51
0.85
NOTION OF SINGLE LOT
The homogeneity of lots is given by the front end lot numbers (primary process lot) and not by the date code.
The date code is applied after completion of end of production testing. Parts coming from different lots might have same date
code.
A customer who needs lot homogeneity should mention on his order: SINGLE PRODUCTION LOT
GLOBAL PART NUMBER INFORMATION
New Global Part Numbering: PHR0603Y1003BBT079 (preferred part number format)
P
TYPE
PHR0603
PHR0805
PHR1206
PHR2010
H
R
0
TCR
6
0
3
Y
1
0
0
3
B
B
T
0
PACKAGING
T:
For tape
and reel
(leave blank
for waffle
pack)
7
9
OPTION
Leave
blank
if no
option
Y
= ± 10 ppm/°C
Z
= ± 5 ppm/°C
E
= ± 25 ppm/°C
OHMIC
VALUE
The first three digits are
significant figures and
the last digit specifies the
number of zero to follow.
R designates decimal
point.
Example:
10R0 = 10
Ω
3901 = 3900
Ω
1004 = 1 MΩ
TOLERANCE
L
= ± 0.01 %
P
= ± 0.02 %
W
= ± 0.05 %
B
= ± 0.10 %
TERMINATION
B:
SnPb over
nickel barrier
G:
Gold
Historical Part Number example: PHR 06 03 Y 1003 BB T (will continue to be accepted)
Document Number: 53037
Revision: 29-Jul-09
For technical questions, contact:
sfer@vishay.com
www.vishay.com
63
Space Applications Only
PHR
Vishay Sfernice
ESCC ( ) 4001/023 Qualified High Precision (5 ppm, 0.01 %),
Thin Film Chip Resistors
GLOBAL PART NUMBER INFORMATION
ESCC Code
4
0
0
1
0
2
3
0
1
1
0
TOLERANCE
L
= ± 0.01 %
P
= ± 0.02 %
W
= ± 0.05 %
B
= ± 0.10 %
0
3
B
TCR
1
ESCC SPEC
4001023
VARIANT
0603
= 01 or 05
0805
= 02 or 06
1206
= 03 or 07
2010
= 04 or 08
OHMIC
VALUE
The first three digits are
significant figures and
the last digit specifies
the number of zero to
follow. R designates
decimal point.
Example:
10R0 = 10
Ω
3901 = 3900
Ω
1004 = 1 MΩ
1
= ± 10 ppm/°C
0
= ± 5 ppm/°C
2
= ± 25 ppm/°C
OPTIONS
TIGHTEST TEMPERATURE COEFFICIENT
The “Z” temperature coefficient is intended for 5 ppm/°C in the (+ 22 °C to + 70 °C) temperature range. Vishay/Sfernice offers
option 079 which guarantee 5 ppm/°C in the (- 55 °C to + 155 °C) temperature range. Option 079 has to be ordered along with
Z temperature coefficient.
LOT VALIDATION TESTING
For procurement of qualified components, lot validation testing is not required and shall only be performed if specifically stipulated
in the purchase order.
For procurement of unqualified components, lot validation testing shall be performed as stipulated in the purchase order. The
need for lot validation testing shall be determined by the orderer.
When lot validation testing is required, it shall consist of the performance of one or more of the tests or subgroup test sequences
of chart F4 indicated in the ESA Generic Specification ESCC 4001. The testing to be performed and the sample size shall be as
stipulated in the purchase order. When procurement of more than one component type is involved from a family, range or series,
the selection of representative samples shall also be stipulated in the purchase order.
Lot validation testing will be composed of one LVT charges and LVT samples:
•
Lot validation test charges has to be ordered separately on purchase order.
•
Lot validation samples have to be ordered separately on purchase orderer.
FINAL INSPECTION
If requested by the orderer a final inspection can be performed on site.
Final inspection has to be stipulated separately on purchase order.
LAND PATTERN
in millimeters
G
min.
Z
max.
CHIP SIZE
0603
0705/0805
1206
2010
Z
max.
2.37
2.76
3.91
5.93
G
min.
0.35
0.74
1.85
3.71
X
m
ax
.
X
max.
0.98
1.40
1.73
2.67
Note
•
Suggested land pattern: According to IPC-7351A
www.vishay.com
64
For technical questions, contact:
sfer@vishay.com
Document Number: 53037
Revision: 29-Jul-09
Space Applications Only
PHR
ESCC (
) 4001/023 Qualified High Precision (5 ppm, 0.01 %),
Vishay Sfernice
Thin Film Chip Resistors
STANDARD ELECTRICAL SPECIFICATIONS
VISHAY SFERNICE DESIGNATION
ESA specification applied
Variant number
Power rating at + 70 °C (Pn)
Limiting element voltage (UL)
Ohmic value range
Insulation voltage (Ui)
Temperature coefficient
Tolerance
Temperature range
Soldering temperature (T
sol
)
01 - 05
0.1 W
35 V
Min. 50
Ω
Max. 200 kΩ
100 V
02 - 06
0.125 W
75 V
Min. 50
Ω
Max. 250 kΩ
200 V
PHR 0603
PHR 0805
PHR 1206
ESCC 4001/023
03 - 07
0.25 W
100 V
Min. 50
Ω
Max. 1 MΩ
300 V
04 - 08
0.50 W
150 V
Min. 50
Ω
Max. 3 MΩ
300 V
PHR 2010
± 10 ppm/°C; ± 25 ppm/°C
± 5 ppm/°C (22 °C to 70 °C)
± 0.01 % (R > 250
Ω),
± 0.02 % (R > 100
Ω),
± 0.05 %, ± 0.1 %
- 55 °C to + 155 °C
260 °C, immersion 10 s
MECHANICAL SPECIFICATIONS
Substrate material
Technology
Film
Protection
Terminations
Alumina
Thin Film
Nickel Chromium
with mineral
passivation
Epoxy and Silicon
B type:
SnPb over nickel barrier
for solder reflow
G type:
Gold
POWER DERATING CURVE
RATED POWER
500
2010
250
1206
PACKAGING
Two types of packaging are available: waffle-pack and tape
and reel.
NUMBER OF PIECES PER PACKAGE
SIZE
0603
0805
1206
2010
WAFFLE
PACK
2" × 2"
100
140
60
100
4000
8 mm
TAPE AND REEL
MIN.
MAX.
TAPE
WIDTH
125
100
0
0805
0603
0
70
155
AMBIENT TEMPERATURE IN °C
EXTENDED FEATURES
You may consult VISHAY SFERNICE for chip sizes, ohmic
values and tolerances outside of the qualified range.
PERFORMANCE
TEST
Short time overload
Rapid temperature change
Soldering (thermal shock)
Terminal strength:
adhesion bend strength of
end plated facing
Climatic sequence
Load life
High temperature
exposure
Document Number: 53037
Revision: 29-Jul-09
CONDITIONS
U
= 6.25 x Pn x Rn/2s
U
max.
< 2 UL
- 55 °C/+ 155 °C 5 cycles
CEI 66-2-14 Test Na
REQUIREMENTS
ESA/SCC 4001/023
± 0.05 % Rn + 0.05
Ω
MIL-PRF-55342G
0.10 %
TYPICAL
± 0.01 %
± 0.01 %
± 0.015 % (for 500 cycles)
± 0.005 %
± 0.01 %
± 0.02 %
Insulation resistance > 1 GΩ
± 0.02 %
Insulation resistance > 1 GΩ
± 0.05 %
Insulation resistance > 1 GΩ
www.vishay.com
65
± 0.05 % Rn + 0.05
Ω
0.1 % (for 100 cycles)
-
-
-
0.5 %
± 0.10 %
(duration 1000 h)
260 °C/10 s
CEI 68-2-20 A Test T6 (met. 1A) ± 0.05 % Rn + 0.05
Ω
CEI 115-1 Clause 4.32
CEI 115-1 Clause 4.33
CEI 67-2-1/CEI 68-2-2
CEI 67-2-13/CEI 68-2-30
2000 h Pn at + 70 °C
90’/30’ cycle
2000 h Pn at + 155 °C
CEI 68-2-20A Test B
± 0.05 % Rn + 0.05
Ω
± 0.10 % Rn + 0.05
Ω
± 0.15 % Rn + 0.05
Ω
± 0.15 % Rn + 0.05
Ω
For technical questions, contact:
sfer@vishay.com
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
www.vishay.com
1
微控制器 MCU
