PI2EQX4402D
2.5 Gbps x2 Lane Serial PCI Express Repeater/Equalizer
with Signal Detect feature
Features
•
•
•
•
•
•
•
•
•
•
•
Two High Speed PCI Express lanes
Supports PCI Express data rates (2.5 Gbps) on each lane
Adjustable Transmiter De-Emphasis & Amplitude
Adjustable Receiver Equalization
Input Signal Level Detect & Output Squelch on all Channels
Two Spread Spectrum Reference Clock Buffer Outputs
100Ω Differential CML I/O’s
Low Power (100mW per Channel)
Standby Mode – Power Down State
V
DD
Operating Range: 1.8V +/-0.1V
Packaging (Pb-free & Green): 84-ball LFBGA (NB84)
Description
Pericom Semiconductor’s PI2EQX4402D is a low power,
PCI Express compliant signal Re-Driver. The device provides
programmable equalization, amplification, and de-emphasis
by using 7 select bits, SEL[0:6], to optimize performance
over a variety of physical mediums by reducing Inter-symbol
interference. PI2EQX4402D supports four 100 Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides
fl
exibility with
signal integrity of the PCI Express signal before the Re-Driver.
Whereas the integrated de-emphasis circuitry provides
fl
exibility
with signal integrity of the PCI Express signal after the Re-
Driver.
A low-level input signal detection and output squelch function
is provided for all four channels. Each channel operates fully
independantly. When a channel is enabled (EN_x=1) and
operating, that channel input signal level (on xl+/-) determines
whether the output is enabled. If the innput level of the channel
falls below the active threshold level (Vth-) then the output driver
switches off, and the pin is pulled to VDD via a high impedance
resistor.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX4402D also provides power management Stand-by mode
operated by an Enable pin. A differential clock buffer is provided
for test and other system requirements. This clock function is not
used by the data channels.
06-0306
1
PS8873B
11/16/06
PI2EQX4402D
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
with Signal Detect feature
Block Diagram
LVCMOS
SD_x
B
VDD
BO+
BO–
GND
VDD
DO+
DO–
GND
SD_C
SD_D
VDD
VDD
GND
SEL0_C
SEL0_D
SEL1_C
VDD
AI+
AI–
GND
VDD
CI+
CI–
GND
VDD
CKIN+
CKIN–
GND
IREF
SEL1_A SEL2_A SEL3_A SEL5_A
SEL1_B SEL2_B SEL3_B
SEL5_B
VDD
BI+
BI–
GND
VDD
DI+
DI–
GND
EN_C
EN_D
GND
GND
GND
SEL6_C
SEL6_D
SEL4_D
VDD
AO+
AO–
GND
VDD
CO+
CO–
GND
Pin Description (Top View)
1
A
SD_A
2
SD_B
3
SEL0_A
4
5
6
7
SEL6_A
8
SEL6_B
9
EN_A
10
EN_B
SEL0_B SEL4_A SEL4_B
CML
CML
xl+
Equalizer
xl-
Limiting
Amp
xO-
xO+
C
D
E
F
84-Ball LFBGA
Power
Management
SEL[3:4]_x SEL[5:6]_x
G
H
CKIN-
CKIN+
Buffer
EN_CLK
IREF
OUT0-
OUT0+
OUT1-
OUT1+
J
K
SEL2_C SEL2_D SEL3_D
EN_CLK SEL1_D SEL3_C SEL4_C
OUT0+ OUT0– OUT1+ OUT1– SEL5_C SEL5_D
06-0306
2
PS8873B
11/16/06
PI2EQX4402D
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
with Signal Detect feature
Pin Description
Pin #
B1, F1, D2, E2,
B3, F3, H4, B8,
F8, B10, F10
C3
D3
E1, J1, F2, E3, J3,
H7, E8, J8, D9,
E9, F9, E10, J10
C8
D8
G3
H3
G8
H8
A3, B4, B5
A4, C4, C5
G2, J2, J4
H2, K2, J5
B6, A5
C6, A6
K3, K4
J6, J9
B7, A7
C7, A8
K9, G9
K10, H9
C10
D10
C1
D1
G10
H10
06-0306
Pin Name
V
DD
AI+
AI-
GND
BI+
BI-
CI+
CI-
DI+
DI-
SEL[0:
2]_A
SEL[0:2]_B
SEL[0:2]_C
SEL[0:2]_D
SEL[3:4]_A
SEL[3:4]_B
SEL[3:4]_C
SEL[3:4]_D
SEL[5:6]_A
SEL[5:6]_B
SEL[5:6]_C
SEL[5:6]_D
AO+
AO-
BO+
BO-
CO+
CO-
I/O
PWR
I
I
PWR
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
1.8V Supply Voltage
Description
Positive CML Input Channel A with internal 50Ω pull down during normal operation
(EN_A=1). When EN_A=0, this pin is high impedance.
Negative CML Input Channel A with internal 50Ω pull down during normal operation
(EN_A=1). When EN_A=0, this pin is high impedance.
Supply Ground
Positive CML Input Channel B with internal 50Ω pull down during normal operation
(EN_B=1). When EN_B=0, this pin is high impedance.
Negative CML Input Channel B with internal 50Ω pull down during normal operation
(EN_B=1). When EN_B=0, this pin is high impedance.
Positive CML Input Channel C with internal 50Ω pull down during normal operation
(EN_C=1). When EN_C=0, this pin is high impedance.
Negative CML Input Channel C with internal 50Ω pull down during normal operation
(EN_C=1). When EN_C=0, this pin is high impedance.
Positive CML Input Channel D with internal 50Ω pull down during normal operation
(EN_D=1). When EN_D=0, this pin is high impedance.
Negative CML Input Channel D with internal 50Ω pull down during normal operation
(EN_D=1). When EN_D=0, this pin is high impedance.
Selection pins for equalizer (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Selection pins for amplifier (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Selection pins for De-Emphasis (See De-Emphasis Configuration Table)
w/ 50KΩ internal pull up
Positive CML Output Channel A internal 50Ω pull up during normal operation and
2KΩ pull up otherwise.
Negative CML Output Channel A with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Positive CML Output Channel B with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Negative CMLOutput Channel B with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Positive CMLOutput Channel C with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Negative CMLOutput Channel C with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
3
PS8873B
11/16/06
PI2EQX4402D
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
with Signal Detect feature
Pin Description
(Continued)
Pin #
GI
HI
A9, A10, B9, C9
H6
H5
K5, K6
K7, K8
J7
K1
Pin Name
DO+
DO-
EN_
[A,B,C,D]
CKIN-
CKIN+
OUT0+,
OUT0-
OUT1+,
OUT1-
IREF
EN_CLK
I/O
O
O
I
I
I
O
Differential Reference Clock Output
O
O
I
External 475Ω resistor connection to set the differential output current
Enable output clock pin with internal 50kΩ pull up resistor. When EN_CLK is
LVCMOS high level, the clock output operates normally. When EN_CLK = low,
the clock outputs are turned off for power savings. A clock is not required by the
data channels for operation.
Signal detected, channels A, B, C, D. Indicated a valid signal level on the channels
input pin pair when active high. When low, SD indicates the input signal level is
below the signal detect threshold level.
Description
Positive CMLOutput Channel D with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Negative CMLOutput Channel D with internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
EN_[A:D] is the enable pin with internal 50KΩ pull up resistor. A LVCMOS high
provides normal operation. A LVCMOS low selects a low power down mode.
Differential Input Reference Clock
A1, A2, B2, C2
SD_x
N/A
Inputs
EN_[A, B, C, D]
High
Low
Outputs
O+ / O-
Normal output
No output
Inputs
EN_CLK
High
Low
Clock Outputs
Clock output
No clock output
Output Swing Control
SEL3_[A:D]
0
0
1
1
SEL0_[A:D]
0
0
0
0
1
1
1
1
SEL4_[A:D]
0
1
0
1
SEL1_[A:D]
0
0
1
1
0
0
1
1
Swing
1x
0.8x
1.2x
1.4x
SEL2_[A:D]
0
1
0
1
0
1
0
1
Output De-emphasis Adjustment
SEL5_[A:D]
0
0
1
1
SEL6_[A:D]
0
1
0
1
De-emphasis
0dB
-2.5dB
-3.5dB
-4.5dB
Equalizer Selection
Compliance Channel
No Equalization
[0:1.5dB] @ 1.25 GHz
[0:2.5dB] @ 1.25 GHz
[0:3.5dB] @ 1.25 GHz
[0:4.5dB] @ 1.25 GHz
[0:5.5dB] @ 1.25 GHz
[0:6.5dB] @ 1.25 GHz
[0:7.5dB] @ 1.25 GHz
06-0306
4
PS8873B
11/16/06
PI2EQX4402D
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
with Signal Detect feature
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature........................................................ –65°C to +150°C
Supply Voltage to Ground Potential ................................... –0.5V to +2.5V
DC SIG Voltage..........................................................–0.5V to V
DD
+0.5V
Current Output ................................................................-25mA to +25mA
Power Dissipation Continous ......................................................... 800mW
Operating Temperature.............................................................. 0 to +70°C
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this speci
fi
cation is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
AC/DC Electrical Characteristics for 2.5 Gbps Quad Repeater/Equalizer
(V
DD
= 1.8 ±0.1V)
Symbol
Ps
Parameter
Supply Power
Latency
CML Receiver Input
RL
RX
Return Loss
Differential Input Peak-to-
V
RX-DIFFP-P
peak Voltage
AC Peak Common Mode
V
RX-CM-ACP
Input Voltage
V
TH
-
Signal Detect Threshold
DC Differential Input
Z
RX-DIFF-DC
Impedance
DC Input Impedance
Z
RX-DC
Equalization
J
RS
J
RM
Residual Jitter
(1,2)
Random Jitter
(1,2)
Total Jitter
Deterministic jitter
1.5
0.3
0.2
Ulp-p
psrms
Conditions
EN = LVCMOS Low
EN = LVCMOS High
From input to output
Min.
Typ.
Max.
0.1
0.6
Units
W
ns
2.0
50 MHz to 1.25 GHz
0.175
12
1.200
150
dB
V
mV
mV
Ω
E
N_X
= High
80
40
120
100
50
175
120
60
Notes
1. K28.7 pattern is applied differentially at point A as shown in Figure 1.
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or
its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at
0V at point C of Figure 1.
06-0306
5
PS8873B
11/16/06
PCB设计
