A product Line of
Diodes Incorporated
PI3PCIE3442
3.3V PCI Express® 3.0 2-Lane Exchange Switch
Features
ÎÎ
Differential Channel (2-lane) Exchange
8
ÎÎ
PCI Express® 3.0 performance, 8.0 Gbps
ÎÎ
Bi-directional operation
ÎÎ
Low Bit-to-Bit Skew: 10ps (between ± signals)
ÎÎ
Low Crosstalk: -29dB @ 2.5GHz (5Gbps)
Description
Pericom semiconductor’s PI3PCIE3442 is a differential exchange
switch featuring pass-through pinout. It supports two full PCI
Express® lanes operating at 8.0Gbps PCIe® 3.0 performance.
With the select control input low, Port A connects to Port B, and
Port C connects to port D for an 8-channel differential pass-
though. When the select control input is high Port A connects to
Port D, and Port B connects to Port C.
-20dB @ 4.0GHz (8Gbps)
ÎÎ
Low Insertion Loss: -1.1dB @ 2.5GHz (5Gbps)
ÎÎ
DD
Operating Range: 3.3V ±10%
V
ÎÎ
ESD Tolerance: 2kV HBM
ÎÎ
Packaging (Pb-free & Green):
-1.45dB @ 4.0GHz (8Gbps)
ÎÎ
Industrial Temperature Range: -40
o
C to 85
o
C
Application
Switching 4 lanes of DP1.2 from PC/Notebook/Tablet to Display
monitor
à
42-contact, TQFN (ZH42), 3.5x9mm.
à
40-contact, TQFN (ZL40), 3x6mm.
Truth Table
Function
Ax = Bx
Cx = Dx
Ax = Dx
Cx = Bx
Ax, Bx, Cx, Dx = Hi-Z (disconnect)
Block Diagram
SEL
0
1
x
OE#
0
0
1
OE#
SEL
A0+
A0-
C0+
C0-
B0+
B0-
D0+
D0-
B1+
B1-
A1+
A1-
C1+
C1-
A2+
A2-
C2+
C2-
A3+
A3-
C3+
C3-
D1+
D1-
B2+
B2-
D2+
D2-
B3+
B3-
D3+
D3-
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A product Line of
Diodes Incorporated
PI3PCIE3442
Pin Diagram 42-TQFN
GND
VDD
VDD
OE#
Pin Diagram 40-TQFN
GND
37
OE#
A0+
B0+
36
A0-
B0-
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
19
16
17
18
20
D3+
D0+
D0-
B1+
B1-
D1+
D1-
VDD
GND
B2+
B2-
D2+
D2-
B3+
B3-
41
42
40
39
A0-
C0+
C0-
A1+
A1-
C1+
C1-
SEL
A2+
A2-
C2+
C2-
A3+
A3-
C3+
C3-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
20
18
21
16
17
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
B0-
D0+
D0-
B1+
B1-
D1+
D1-
VDD
B2+
B2-
D2+
D2-
B3+
B3-
D3+
D3-
C0+
C0-
A1+
A1-
C1+
C1-
SEL
A2+
A2-
C2+
C2-
A3+
A3-
C3+
1
2
3
4
5
6
7
8
9
GND
40
15
39
C3-
GND
10
11
12
13
14
38
VDD
A0+
1
38
B0+
GND
GND
GND
VDD
VDD
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GND
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D3-
06/13/16
A product Line of
Diodes Incorporated
PI3PCIE3442
Application Diagram
PI3PCIE3442
OE#
SEL
A0+
A0-
C0+
C0-
A1+
A1-
C1+
C1-
A2+
A2-
C2+
C2-
B0+
B0-
DA0-DA3
DA0-DA3
D0+
D0-
B1+
B1-
D1+
D1-
B2+
B2-
D2+
D2-
B3+
B3-
D3+
D3-
DAX or DBX
AUXX, HPDX
CAB_DETX
DP conn
A
DB Monitor A
CAB_DETA
DP Source
A
DB0-DB3
AUXB, HPDB
CAB_DETB
DP Source
B
A3+
A3-
C3+
C3-
DBX or DAX
AUXX, HPDX
CAB_DETX
DP conn
B
DB Monitor B
OUTB0
OUTB1
ENB
INB
SBO
SBI
SAI
SAO
ENB
INB
OUTB0
OUTB1
SBO
PI3DBS3224
PI3DBS3224
SBI
SAI
SAO
OUTA0
OUTA1
INA
ENA
OUTA0
OUTA1
INA
ENA
Generic 2 x 2 DP1.2 Switching Using PI3PCIE3442 (3x6mm 40 pad QFN)
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A product Line of
Diodes Incorporated
PI3PCIE3442
Pin Description (42-TQFN)
Pin #
1
2
5
6
10
11
14
15
38
37
34
33
29
28
25
24
3
4
7
8
12
13
16
17
36
35
32
31
27
26
23
22
41
9
18, 20, 30, 40, 42
19, 21, 39, Center Pad
Pin Name I/O
A0+
A0–
A1+
A1–
A2+
A2–
A3+
A3–
B0+
B0−
B1+
B1−
B2+
B2−
B3+
B3−
C0+
C0–
C1+
C1–
C2+
C2–
C3+
C3−
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
OE#
SEL
V
DD
GND
I
I
Pwr
Pwr
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Signal I/O, Channel 0, Port A
Signal I/O, Channel 1, Port A
Signal I/O, Channel 2, Port A
Signal I/O, Channel 3, Port A
Signal I/O, Channel 0, Port B
Signal I/O, Channel 1, Port B
Signal I/O, Channel 2, Port B
Signal I/O, Channel 3, Port B
Signal I/O, Channel 0, Port C
Signal I/O, Channel 1, Port C
Signal I/O, Channel 2, Port C
Signal I/O, Channel 3, Port C
Signal I/O, Channel 0, Port D
Signal I/O, Channel 1, Port D
Signal I/O, Channel 2, Port D
Signal I/O, Channel 3, Port D
Output Enable, active low. When OE# = 0 the device I/O is enabled. When OE#=1,
all I/O are high impedance
Operation mode Select
(when SEL=0: A→B, C→D, when SEL=1: A→D, C→B)
3.3V ±10% Positive Supply Voltage
Power ground
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A product Line of
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Pin Description (40-TQFN)
Pin #
39
40
3
4
8
9
12
13
36
35
32
31
26
25
22
21
1
2
5
6
10
11
14
16
34
33
30
29
24
23
20
19
38
7
17, 28
15, 18, 27, 37, Center
Pad
PI3PCIE3442
Description
Signal I/O, Channel 0, Port A
Signal I/O, Channel 1, Port A
Signal I/O, Channel 2, Port A
Signal I/O, Channel 3, Port A
Signal I/O, Channel 0, Port B
Signal I/O, Channel 1, Port B
Signal I/O, Channel 2, Port B
Signal I/O, Channel 3, Port B
Signal I/O, Channel 0, Port C
Signal I/O, Channel 1, Port C
Signal I/O, Channel 2, Port C
Signal I/O, Channel 3, Port C
Signal I/O, Channel 0, Port D
Signal I/O, Channel 1, Port D
Signal I/O, Channel 2, Port D
Signal I/O, Channel 3, Port D
Output Enable, active low. When OE# = 0 the device I/O is enabled. When OE#=1,
all I/O are high impedance
Operation mode Select (when SEL=0: A→B, C→D, when SEL=1: A→D, C→B)
3.3V ±10% Positive Supply Voltage
Power ground
Pin Name I/O
A0+
A0–
A1+
A1–
A2+
A2–
A3+
A3–
B0+
B0−
B1+
B1−
B2+
B2−
B3+
B3−
C0+
C0–
C1+
C1–
C2+
C2–
C3+
C3−
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
OE#
SEL
V
DD
GND
I
I
Pwr
Pwr
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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