21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C200-C, PI6C200P, PI6C200-3
TM
Direct Rambus Clock Generator
Features
•
Provides a 400MHz differential clock source for Direct Rambus
memory systems to transfer data at up to 1.6 Gbytes/second
•
Allows synchronization of the data transfer across the
boundary of two different clock domains: the Rambus Channel
clock domain and the external system clock domain, both with
minimal latency.
•
Provides two power-saving modes for mobile and power-
sensitive applications:
Clk
STOP
Mode: only the clock output driver is disabled.
Power Down Mode: the entire chip is powered down.
•
Supports tracking of Spread Spectrum Clocking (SSC)
for EMI suppression
•
Supports a Rambus Channel clock independent of an external
system clock
•
3.3V power supply
•
Low cycle-to-cycle jitter
•
Packaged in Plastic 24-pin 150-mil QSOP Package (Q).
Description
Pericoms series PI6C200 Direct Rambus Clock Generator (DRCG)
family provides the high-speed clock signal source required for the
Direct Rambus memory system.
A Direct Rambus memory system transfers data in the Rambus
Channel at both rising and falling edges of a clock pulse. At 400
MHz clock speed, 800 MHz data transfers can occur. Since there are
two bytes per data transfer, a data transfer rate of up to 1.6 Gbytes/
second can be achieved.
The Reference Clock Input (RefClk) is provided by the external
system clock generator: Pericoms PI6C133. The PI6C200 gener-
ates a differential clock output to drive the Rambus Channel. Output
clock frequency is determined by the RefClk input frequency and
the frequency multiplier selected. For example, if the RefClk input
frequency is 66.6 MHz , the output clock frequency is 400 MHz
when frequency multiplier = 6 is selected.
The Rambus Channel clock and the external system clock are
running at different frequencies. These two clocks must be synchro-
nized to avoid a significant latency incurred during the data transfer
across the boundary of these two different clock domains. To
synchronize data transfer across the boundary of the two different
clock domains, the PI6C200 adjusts the timing phase of the Rambus
Channel clock, resulting in minimal latency.
There are two power saving modes. If the output driver is disabled,
fast transitions between clock-on and clock-off states are allowed.
When minimal power dissipation is desired, the entire PI6C200
chip can be powered down.
When the RefClk input clock uses Spread Spectrum clocking for
EMI suppression, the PI6C200 tracks the RefClk input frequency
to assure proper operation. The RefClk input clock jitter is also
attenuated.
The PI6C200 offers flexibile Rambus Channel clock frequencies
ranging from 267 MHz to 400 MHz. Several PLL bypass modes are
provided for various testing purposes.
The multiplication tables for the DRCG-C, DRCG-P, and DRCG-3 are
different. See the functional description for more information.
Pin Configuration
V
DD
IR
RefClk
V
DD
P
GndP
GndI
PClkM
SynClkN
GndC
V
DD
C
V
DD
IPD
StopB
PwrDnB
1
2
3
4
5
6
7
8
9
10
11
12
24-Pin
Q
24
23
22
21
20
19
18
17
16
15
14
13
S0
S1
V
DD
O
GndO
Clk
N/C
ClkB
GndO
V
DD
O
Mult0
Mult1
Gnd
1
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PI6C200-C, PI6C200P, PI6C200-3
Direct Rambus Clock Generator
Pin Description
Pin#
Name
Type
De s cription
Reference voltage of the RefClk Reference Clock input signal. To be connected to the
voltage supply of the RefClk clock output driver at the system clock generator chip CK133.
This reference voltage is used by the PI6C200 to determine the proper threshold trip- point
of the RefClk input signal.
Reference Clock provided by the system clock generator CK133
V
dd
for PLL circuit, 3.3V ±5% supply
Gnd for PLL circuit
Gnd for Control Inputs
Phase Detector Input from Memory Control ASIC
Gnd for Phase Aligner
V
DD
for Phase Aligner; 3.3V ±5% supply
Reference voltage for phase detector inputs (PClkM, SynClkN) and Stop B. To be connected to
the voltage supply of Memory Control ASIC. This reference voltage is used by the PI6C200 to
determine the proper threshold trip- point of the phase detector inputs and stop B.
Disable the differential output drivers of Clk and ClkB to a voltage level V
X,STOP
set by internal
resistor divider. Active Low; 3.3V CMOS input signal
Power down the entire PI6C200 chip. Active low; 3.3V CMOS input signal
Ground
PLL Multiplier Select; 3.3V CMOS input signal
V
DD
for Clock Outputs; 3.3V ±5% supply
Ground for Clock Outputs
Output Clock; Complement; Connect to Rambus Channel
Not Used; No Connection; Floating
Out
Gnd
Pwr
In
In
Output Clock; Connect to Rambus Channel
Ground for Clock Outputs
Vdd for Clock Outputs; 3.3V ±5% supply
Mode Control; 3.3V CMOS input signal
1
V
DD
IR
RefV
2
3
4
5
6
7
8
9
10
Refclk
V
DD
P
GndP
GndI
PClkM
SynClkN
GndC
V
DD
C
V
DD
IPD
In
Pwr
Gnd
Gnd
In
In
Gnd
Pwr
RefV
11
12
13
14
15
16
17
18
19
20
21
22
23
24
StopB
PwrDnB
Gnd
Mult 1
Mult 0
V
DD
O
GndO
ClkB
N/C
Clk
GndO
V
DD
O
S1
S0
In
In
Gnd
In
In
Pwr
Gnd
Out
2
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V
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C200-C, PI6C200P, PI6C200-3
Direct Rambus Clock Generator
PwrDnB S0
Test MUX
S1 StopB
DRCG-P Multiplication Table
The multiplication factor A/B is determined by the selection signals
Mult0 and Mult1:
Bypass MUX
PLLClk
RefClk
B
A
PLL
Phase
Aligner
Phase
Detector
V
BypClk
Differential
Output
Buffer
Clk
ClkB
M ult0
0
0
1
1
M ult1
0
1
1
0
A
9
6
8
16
B
2
1
1
3
M ultiplication
Factor A/'B
9/2
6
8
16/3
PAClk
2
Mult0
Mult1
PClkM SynClkN
Figure 1. Direct Rambus Clock Generator Block Diagram
Functional Description
In figure 1, the PLL multiplier consists of a PLL, a prescalar B, and
a counter A. The PLL Multiplier multiplies the frequency of the
Refclk reference clock by a factor to generate the desired frequency
for Clock Output, as following:
Clock Output frequency = Refclk freq x (A/B)
DRCG-C Multiplication Table
The multiplication factor A/B is determined by the selection signals
Mult0 and Mult1:
M ult0
0
0
1
1
M ult1
0
1
1
0
A
4
6
8
8
V
DRCG-3 Multiplication Table
The multiplication factor A/B is determined by the selection signals
Mult0 and Mult1:
M ult0
0
0
1
1
M ult1
0
1
1
0
A
4
6
8
16
B
1
1
1
3
M ultiplication
Factor A/'B
4
6
8
16/3
B
1
1
1
3
M ultiplication
Factor A/'B
4
6
8
8/3
The Phase Detector compares the phase difference of two inputs,
PClkM and SynClkN, and based on their phase difference, drives
the Phase Aligner to delay the PLL output by that difference. This
phase alignment minimizes the latency of data transfer at Rambus
Memory Controller.
Under normal operational mode, the Differential Output Buffer
receives the clock signal from the Phase Aligner to drive a
differential clock output. The buffer driver is impedance-matched
to the Rambus Channel transmission line.
The S0 and S1 input pins select the mode of operation:
M ode
Normal
Bypass
Test
O utput
Test
3
S0
0
1
1
0
S1
0
0
1
1
Clk
Output
PAClk
PLLClk
RefClk
Hi- Z
ClkB
Output
PAClkB
PLLClkB
RefClkB
Hi- Z
PS8414
11/29/99
Controller
(RMC)
SynClk/N
Pclk/M
V
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C200-C, PI6C200P, PI6C200-3
Direct Rambus Clock Generator
System
Clock
Source
RefClk
PI6C200-U
Direct Rambus
Clock Generator
(DRCG)
Bus Clock
Rambus
Memory
Rambus
ASIC Cell
(RAC)
RDRAMs
Pclk
SynClk
/4
DLL
V
Gear Ratio
Logic
M N
Memory Control ASIC
Figure 2. System Clock Architecture
Typical System Clock Configuration
Figure 2 shows the interconnection of the System Clock Generator,
the PI6C200 DRCG, Rambus Memory Control ASIC, and Rambus
memory. The Memory Control ASIC contains the Rambus Access
Cell(RAC), the Rambus Memory Controller(RMC), and the logic
to support synchronizing the Channel Bus Clock with the Memory
Controller Clock.
The main system clock generator drives both the system clock
(Pclk) to the ASIC, and the reference clock (RefClk) to the PI6C200.
RefClk may or may not be the same frequency as PClk. A PLL inside
the PI6C200 multiplies the RefClk input to generate the desired
frequency for the Bus Clock to drive the Rambus channel through
a terminated transmission line. At the mid-point of the channel, the
RAC senses that the Bus Clock is using its own DLL. This is
followed by a fixed divide-by-4 circuit that generates SynClk.
PClk is the clock used by the RMC in the ASIC. SynClk is the clock
used at the ASIC at the interface of RAC. The frequency of SynClk
is not the same as PClk. By dividing the PClk and SynClk with
different M and N divisors, the Gear Ratio Logic matches the
frequencies at the RMC/RAC boundary.
4
For example:
If PClk = 133MHz and Bus Clock = 400MHz
(SynClk = 100MHz), the gear ratio of M = 4
and N = 3 gives PClk/M = SynClk/N = 33 MHz.
PClk =
133MHz
As described in the previous section, the Phase Detector in the
PI6C200 compares the phases of PClk/M and SynClk/N, then
drives the Phase Aligner to adjust the phase of the PI6C200 output
clock. Adjusting the phase of the Bus clock adjusts the phase of
SynClk and also the phase of SynClk/N to match the phase of PClk/
M. When the clock signals at the boundary of RMC and RAC are
matched and phase-aligned, data transfers between the PClk do-
main and the SynClk domain will occur across this boundary
without additional latency.
PS8414
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C200-C, PI6C200P, PI6C200-3
Direct Rambus Clock Generator
Table 1. Frequencies, Counter Dividers, and Gear Ratios
Bus
Clock
267
300
400
267
400
SynClk
67
75
100
67
100
A
8
6
8
4
6
B
1
1
1
1
1
M
2
8
4
4
8
N
2
6
4
2
6
Ratio
1.0
1.33
1.0
2.0
1.33
Fre que ncy at
Phas e D e te ctor
33
12.5
25
33
16.7
System Architecture without Gear ratio Logic
Some system may not require synchronization of the Rambus
Channel clock to another system clock. In this case, the Memory
Control ASIC does not use the Gear Ratio Logic. Since the Phase
Aligner part of the DRCG is not used, the Phase Aligner inputs
(PClkM and SynClkN) must be tied to ground and not left floating.
Because the resulting SynClk and PClk signals are not aligned, data
must be retimed (may use FIFOs) at the PClk/SynClk boundary.
The PI6C200 has three fundamental operating states, as shown in
Figure 3 and Table 2.
In Power Down mode, the PI6C200 is powered down with the
control signal PwrDnB=0.
In Clk Stop mode (StopB=0), the PI6C200 internal circuit is ON,
but the clock output is disabled.
Table 2. Control Signals for PI6C200 States
State
VDD turn-on
G
PwrD nB
Pin
0
1
1
StopB
Pin
X
0
1
PI6C200
Inte rnal
Circuit
O ff
On
On
Clk
Output
Buffe r
Ground
Disabled
Enabled
Powerdown
(1)
Clock Stop
(2)
F
E
D
VDD turn-on
Clk Stop
C
H
Normal
B
A
VDD turn-on
Powerdown
Normal
Notes:
1. The S0 and S1 input control signals must be stable before
power is applied to the device, and can only be changed in
Power Down mode.
2. During ClkStop mode: The V
DD
IPD reference supply may
remain ON or may be grounded. And, the V
DD
IR reference
supply must remain ON.
Figure 3. PI6C200 State Diagram
5
PS8414
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