1. Stresses greater then those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the this specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. θJA and θJB values are determined for a 4-layer board in still-air, unless otherwise stated.
13-0019
2
PS9002B
12/12/12
PI6C22409
2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs
DC Electrical Characteristics
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
IN
= 0V
V
IN
= V
DD
I
OL
= 12mA
V
DD
= 2.5V, I
OH
= –12mA
V
DD
= 3.3V, I
OH
= –12mA
Unloaded outputs 66 MHz
V
DD
= 3.3V
V
DD
= 2.5V
1.8
2.4
32
mA
2.0
1.7
50
125
0.4
0.5
V
µA
Min.
Max.
0.8
0.7
V
Units
13-0019
3
PS9002B
12/12/12
PI6C22409
2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs
AC Electrical Characteristics
Parameter
F
O
BW
t
DC
t
R
t
F
t
sk(o)
t
0
t
SK(D)
Description
Output Frequency
Bandwidth for PLL
Duty Cycle
(4)
Rise Time
(1)(4)
Fall Time
(1)(4)
Output to Output skew
(1)
Delay, REF Rising Edge to
CLKOUT Rising Edge
(1)
(3)
Test Conditions
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
Measured at V
DD
/2, 10 pF load
For 3.3V: Measured between 0.8V and 2.0V; @10pF
For 2.5V: Measured between 0.6V and 1.8V; @10pF
For 3.3V: Measured between 0.8V and 2.0V; @10pF
For 2.5V: Measured between 0.6V and 1.8V; @10pF
All Outputs Equally Loaded
Measured at V
DD
/2, 66MHz
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
Min.
10
10
Typ.
Max.
200
220
Units
MHz
MHz
MHz
0.8
1.5
45
50
55
1
1.8
1
1.8
100
100
-100
-200
-300
0
0
47
42
45
40
63
83
51
66
39
28
39
27
48
75
43
60
100
200
+300
110
90
100
80
120
130
115
115
90
60
85
55
85
90
75
80
1
%
ns
(2)(5)
ps
Device-to-device skew
(1)
Measured at V
DD
/2 on CLKx pins of device
15pF load, >66MHz,
standard drive
15pF load, >66MHz,
high drive
30pF load, >66MHz,
standard drive
30pF load, >66MHz,
high drive
15pF load, >66MHz,
standard drive
15pF load, >66MHz,
high drive
30pF load, >66MHz,
standard drive
30pF load, >66MHz,
high drive
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
t
JIT
Cycle-to-Cycle Jitter
ps
t
PJ
Period Jitter (Peak)
ps
t
LOCK
PLL Lock time
(1)
Stable power supply, valid clocks presented on
CLKOUT pin
ms
Note:
1. See Switching Waveforms
2. All clock output should have the same loading to achieve zero delay between the input and outputs and zero output-to-output skew. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust to input-to-output delay. If input-to-output delay adjustments are needed, the CLKOUT load may be
changed to vary the delay between the REF input to the clock outputs. Output-to-output skew includes CLKA1-4 and CLKB1-4.
3. Specifications are guaranteed by design and not production tested.
4. Measured at 100MHz.
5. Measured with 16-Pin SOIC package
13-0019
4
PS9002B
12/12/12
PI6C22409
2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs
FPGA/CPLD
