PI6LC48C21
Single Output LVCMOS Clock Generator
Features
ÎÎ
Single
Description
The PI6LC48C21 is a single LVCMOS output synthesizer opti-
mized to generate Ethernet reference clock frequencies and is a
member of Pericom’s HiFlex family of high performance clock
solutions. Using a 25MHz crystal, It can generate 125MHz with
very low phase jitter.
It is ideal for Ethernet interface in all kind of systems.
LVCMOS output
ÎÎ
Supports 125MHz or 130MHz output frequencies
ÎÎ
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.15ps (typical)
(12kHz – 20MHz): 0.33ps (typical)
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RMS phase jitter @ 125MHz, using a 25MHz crystal
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Full 3.3V or 2.5V supply modes
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Industrial ambient operating temperature
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Available in lead-free package: 8-TSSOP
Applications
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Networking systems
Block Diagram
Pin Configuration
OE
XTAL_IN
XTAL_OUT
OSC
VDDA
PFD
VCO
/5
CLK
1
2
3
4
8
7
6
5
VDD
CLK
GND
NC
OE
XTAL_OUT
XTAL_IN
/25
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PI6LC48C21
Rev. B
08/04/15
Single Output LVCMOS Clock Generator
Pinout Table
Pin No.
1
2
3, 4
5
6
7
8
PI6LC48C21
Pin Name
VDDA
OE
XTAL_OUT,
XTAL_IN
NC
GND
CLK
VDD
I/O Type
Power
Input
Crystal
Pull-up
Description
Analog Power Supply
High: Output enabled; Low: Output high impedence
Crystal Input and Output
No Connect
Power
Output
Power
Ground
Output Clock
Power Supply
Typical Crystal Requirement
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance
(ESR)
Shunt Capacitance
Drive Level
22.4
Minimum
Typical
Fundamental
25
Maximum
27.2
50
7
1
Units
MHz
Ω
pF
mW
Recomended Crystal Specification
Pericom recommends:
a) FL2500047, SMD 3.2x2.5(4P), 25MHz, CL=18pF, +/-20ppm. http://www.pericom.com/pdf/datasheets/se/FL.pdf
b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm. http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2600018, SMD 3.2x2.5(4P), 26MHz, CL=18pF, +/-20ppm. http://www.pericom.com/pdf/datasheets/se/FL.pdf
Output Frequency
Crystal Frequency (MHz)
25
26
125
130
Output Frequency (MHz)
Pin Characteristics
Symbol
C
JN
R
PULLUP
R
OUT
Parameter
Input Capacitance
Pull up resistor
Output Impedence
Minimum
Typical
4
51
15
Maximum
Units
pF
kΩ
Ω
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PI6LC48C21
Rev. B
08/04/15
Single Output LVCMOS Clock Generator
Maximum Ratings
(Over operating free-air temperature range)
Storage Temperature.............................................. -65ºC to+155ºC
Ambient Temperature with Power Applied .........-40ºC to+85ºC
3.3V Analog Supply Voltage ......................................-0.5 to +3.6V
ESD Protection (HBM) ......................................................... 2000V
PI6LC48C21
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics
Symbol
V
DD,
V
DDA
V
DD,
V
DDA
I
DD
I
DDA
Power Supply DC Characterisitcs,
(V
DD
= V
DDA
, T
A
= -40 to 85ºC)
Parameter
Core, Analog Supply Voltage
Core, Analog Supply Voltage
Power Supply Current
Analog Supply Current
Condition
Min
3.135
2.375
Typ
3.3
2.5
Max
3.465
2.625
45
25
Units
V
V
mA
mA
DC Electrical Characteristics,
(V
DD
= V
DDA
, T
A
= -40 to 85ºC)
Symbol
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
OE
OE
Condition
V
DD
= 3.3V
±5%
V
DD
= 2.5V ±5%
V
DD
= 3.3V ±5%
V
DD
= 2.5V ±5%
V
DD
= 3.3V±5%, I
OH
= -8mA
V
DD
= 2.5V±5%, I
OH
= -4mA
V
DD
= 3.3V±5%, I
OL
= 8mA
V
DD
= 2.5V±5%, I
OL
= 4mA
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
Min
2
1.7
-0.3
-0.3
2.6
90% VDD
Typ
Max
V
DD
+0.3
V
DD
+0.3
0.8
0.7
Units
V
V
V
0.4
10% VDD
5
-150
V
uA
uA
AC Electrical Characteristics,
(V
DD
= V
DDA
, T
A
= -40 to 85ºC)
Symbol
f
OUT
t
jit(Ø)
t
R
/ t
F
o
DC
Parameter
Output Frequency
RMS Phase Jitter,
(Random)
(1)
Output Rise/Fall Time
Output Duty Cycle
Condition
125MHz,
(1.875MHz - 20MHz)
125MHz,
(12kHz - 20MHz)
20% to 80%
Min.
112
Typ.
125
0.15
0.33
Max
136
Units
MHz
ps
ps
250
47
800
53
ps
%
Note:
1.
Please refer to the Phase Noise Plots.
15-0105
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PI6LC48C21
Rev. B
08/04/15
Single Output LVCMOS Clock Generator
LVCMOS Test Circuit
PI6LC48C21
Phase Noise Plot
125MHz
Power Supply Filtering Techniques
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The PI6LC48C21 provides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V
DD
and V
DDA
should be individually connected to the power supply plane through vias, and
0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic V
DD
pin and also shows that V
DDA
requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the V
DDA
pin.
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PI6LC48C21
Rev. B
08/04/15
Single Output LVCMOS Clock Generator
Crystal Input Interface
The clock generator has been characterized with 18pF parallel resonant crystals. The capacitor values shown in the figure below
were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
PI6LC48C21
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram
is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS
signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with
the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resis-
tance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in
half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most
50Ω applications, R1 and R2 can be 100Ω.
This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the
crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal.
V
DD
V
DD
Ro
Rs
50Ω
R1
0.1µF
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
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PI6LC48C21
Rev. B
08/04/15
