PI6PCIEB24
1:4 PCI Express® Clock Driver
Features
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Phase jitter filter for PCIe® 2.0 application
Four pairs of HCSL PCIe 2.0 Differential Clocks
Prop delay <± 250ps (in PLL mode)
Low skew < 50ps
Low jitter < 50ps cycle-to-cycle
< 1 ps additive RMS phase jitter
100 MHz PLL Mode operation
3.3V operation
Packaging (Pb-free and Green):
à
20-Pin 4.0mm x 4.0mm x0.75mm TQFN (ZD20)
Description
Pericom Semiconductor's PI6PCIEB24 is a PCI Express® (PCIe)
2.0 compliant high-speed, low-noise differential clock buffer. The
device distributes the input differential PCIe clock to four differ-
ential pairs of clock outputs with zero delay PLL.
Block Diagram
Pin Configuration
I
REF
V
DD_A
V
DD
SRC
SRC#
OE_0
OUT0
OUT0#
OUT1
OUT1#
SRC
SRC#
OUT2
OUT2#
OUT3
OUT3#
PWRDWN#
PLL
OE_3
16
17
18
19
20
1
2
3
4
5
10
9
8
7
6
15
14
13
12
11
V
DD
OUT0
OUT0#
OE_0
OUT1
OUT3
OUT3#
OE_3
OUT2
OUT2#
V
DD
PWRDWN#
PLL/BYPASS#
V
DD
OUT1#
PLL/BYPASS#
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PS9070A
09/01/10
1:4 PCI Express® Clock Driver
Pin Descriptions
Pin Name
SRC & SRC#
OUT[0:3] & OUT[0:3]#
IREF
V
DD
PWRDWN#
VDD_A
PLL/BYPASS#
OE_0, OE_3
PI6PCIEB24
Type
Input
Output
Input
Power
Input
Power
Input
Input
Pin No
19, 20
2, 3, 5, 6, 12, 11, 15, 14
16
1, 7, 10, 18
9
17
8
4, 13
Description
0.7V Differential SRC input from PI6C410 clock synthesizer
0.7V Differential outputs
External resistor connection to set the differential output current
3.3V Power Supply for Outputs
3.3V LVTTL active LOW input for power down operation
3.3V Power Supply for PLL
When HIGH, PLL is enabled, When LOW, PLL is bypassed.
When HIGH, enables corresponding OUT0, OUT3 respectively.
Ground connection is through the package metal plate underneath.
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PS9070A
09/01/10
1:4 PCI Express® Clock Driver
Functionality
PWRDWN#
1
0
PI6PCIEB24
OUT
Normal
I
REF
×
2
OUT#
Normal
Low
Power Down (PWRDWN# assertion)
PWRDWN#
OUT
OUT#
Figure 1. Power down sequence
When PWRDWN# is asserted (Low), 2xI
REF
current flows through OUT pin.
Power Down (PWRDWN# De-assertion)
Tstable
<1ms
PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
Figure 2. Power down de-assert sequence
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PS9070A
09/01/10
1:4 PCI Express® Clock Driver
Current-mode output buffer characteristics of OUT[0:3], OUT[0:3]#
V
DD
(3.3V ± 5%)
PI6PCIEB24
Slope ~ 1/Rs
R
O
I
OUT
R
OS
Iout
V
OUT
= 0.85V max
0V
0.85V
Figure 2. Simplified diagram of current-mode output buffer
Differential Clock Buffer characteristics
Symbol
R
O
R
OS
V
OUT
Minimum
3000Ω
unspecified
N/A
Maximum
N/A
unspecified
850mV
Current Accuracy
Symbol
I
OUT
Conditions
V
DD
= 3.30 ±5%
Configuration
R
REF
= 475Ω 1%
I
REF
= 2.32mA
Load
Nominal test load for given
configuration
Min.
-12% I
NOMINAL
Max.
+12% I
NOMINAL
I
NOMINAL
refers to the expected current based on the configuration of the device.
Differential Clock Output Current
Board Target Trace/Term Z
100Ω
(100Ω differential
≈
15% coupling ratio)
Reference R, Iref = V
DD
/(3xRr) Output Current
R
REF
= 475Ω 1%,
I
REF
= 2.32mA
I
OH
= 6 x I
REF
V
OH
@ Z
0.7V @ 50
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PS9070A
09/01/10
1:4 PCI Express® Clock Driver
Absolute Maximum Ratings
(Over operating free-air temperature range)
Symbol
V
DD_A
V
DD
V
IH
V
IL
Ts
V
ESD
PI6PCIEB24
Parameters
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
Input High Voltage
Input Low Voltage
Storage Temperature
ESD Protection
Min.
-0.5
-0.5
-0.5
-65
2000
Max.
4.6
4.6
4.6
150
Units
V
°C
V
Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Electrical Characteristics
(V
DD
= 3.3±5%, V
DD_A
= 3.3±5%)
Symbol
V
DD_A
V
DD
V
IH
V
IL
I
IK
I
OH
C
IN
C
OUT
L
PIN
I
DD
I
SS
T
A
Parameters
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current
Output High Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Power Supply Current
Power Down Current
Ambient Temperature
Condition
Min.
3.135
3.135
Max.
3.465
3.465
V
DD
+ 0.3
0.8
+5
15.6
Units
V
DD
0 < V
IN
< V
DD
I
OH
= 6 x I
REF
,
I
REF
= 2.32mA
2.0
V
SS
– 0.3
-5
12.2
3
V
μA
mA
pF
nH
mA
°C
5
6
7
V
DD
= 3.465V, F
CPU
= 100MHz
Driven outputs
-45
200
40
85
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PS9070A
09/01/10
嵌入式系统
