21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVC74A
Fast CMOS 3.3V Dual Positive-Edge-Triggered
D-Type Flip-Flops with Clear & Preset
Product Description
Product Features
• Functionally compatible with LCX family of products
• 1.65V - 3.6V V
CC
supply operation, –40°C to 85°C
• ESD Protection exceeds 2000V, Human Body Model
200V, Machine Model
• Inputs accept up to 5.5V
• Balanced sink and source output drives (24mA)
• Low ground bounce outputs, <0.8V @ 3.3V, 25°C
• Supports live insertion
• Packages available:
– 14-pin 173-mil wide plastic TSSOP (L)
– 14-pin 150-mil wide plastic SOIC (W)
Pericom Semiconductor’s PI74LVC series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving high speed while maintaining low-power
operation.
The PI74LVC74A is a dual positive-edge-triggered D-type flip flop
operating as follows: a low level at preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels of the other
inputs. When PRE and CLR are inactive (HIGH), data at the data (D)
input that meets the setup time requirements is transferred to the
outputs on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to the
rise time of the clock pulse. Following the hold-time interval, data
at the D input can be changed without affecting the levels at the
outputs
Inputs can be driven from either 3.3V or 5.0V devices allowing the
PI74LVC74A to be used as a translator in a mixed 3.3V/5.0V system.
Logic Diagram (each flip-flop)
Pin Configuration
PRE
CLK
C
C
C
TG
C
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
14-Pin
L, W
14
13
12
11
10
9
8
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
Q
Truth Table
C
D
TG
C
CLR
C
TG
C
C
TG
C
Q
PRE
L
H
L
H
H
H
H
L
L
H
H
H
Inputs
CLR
CLK
X
X
X
↑
↑
L
D
X
X
X
H
L
X
Outputs
Q
H
L
H
*
H
L
Q
0
Q
L
H
H
*
L
H
Q
0
Note:
* This configuration is unstable; that is, it does not persist when
PRE or CLR returns to its inactive (HIGH) level.
1
PS8671
03/24/03
PI74LVC74A
Fast CMOS 3.3V Dual Positive-Edge-Triggered
D-Type Flip-Flops with Clear & Preset
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, V
CC
............................................................ –0.5V to 6.5V
Input voltage range, V
I(1)
.............................................................. –0.5V to 6.5V
Output voltage range, V
O(1,2)
............................................. –0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ............................................................... –50mA
Output clamp current, I
OK
(V
O
<0) .......................................................... –50mA
Continuous output current, I
O
................................................................ ±50mA
Continuous current through V
CC
or GND .............................................. ±100mA
Package thermal impedance,
θ
JA(3)
: W package ................................. 113°C/W
L package .................................... 100°C/W
Storage Temperature range, T
stg ................................................................
65°C to 150°C
Notes:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1. The Input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V
CC
is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
PS8671
03/21/03
PI74LVC74A
Fast CMOS 3.3V Dual Positive-Edge-Triggered
D-Type Flip-Flops with Clear & Preset
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Recommended Operating Conditions
(4)
Parame te r
V
CC
De s cription
Supply Voltage
Operating
Data retention only
V
CC
= 1.65V to 1.95V
V
IH
High- level Input Voltage
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 1.65V to 1.95V
V
IL
Low- level Input Voltage
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
I
V
O
Input Voltage
Output Voltage
V
CC
= 1.65V
I
OH
High- level output current
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 1.65V
I
OL
Low- level output current
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
∆
t /
∆
v
M in.
1.65
1.5
0.65 x V
CC
1.7
2.0
M a x.
3.6
Units
0.35 x V
CC
0.7
0.8
0
0
5.5
V
CC
–4
–8
– 12
– 24
4
8
12
24
0
–40
10
85
V
mA
Input transition rise or fall time
Operating free- air temperature
ns/V
°C
T
A
Note:
4. All unused inputs must be held at V
CC
or GND to ensure proper device operation.
3
PS8671
03/21/03
PI74LVC74A
Fast CMOS 3.3V Dual Positive-Edge-Triggered
D-Type Flip-Flops with Clear & Preset
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
DC Electrical Characteristics
(Over Recommended Operating Free-Air Temperature Range, unless otherwise noted)
Parame te rs
Te s t Conditions
I
OH
= –100
µA
I
OH
= –4mA
V
OH
I
OH
= –8mA
I
OH
= –12mA
I
OH
= –24mA
I
OL
= 100µA
I
OL
= 4mA
V
OL
I
OL
= 8mA
I
OL
= 12mA
I
OL
= 24mA
I
I
I
CC
∆I
CC
C
I
V
I
= 5.5
V
or GND
V
I
= V
CC
or GND
I
O
= 0
V
CC
1.65V to 3.6V
1.65V
2.3V
2.7V
3V
3V
1.65V to 3.6V
1.65V
2.3V
2.7V
3V
3.6V
3.6V
2.7V to 3.6V
3.3V
3
M in.
V
CC
–0.2V
1.2
1.7
2.2
2.4
2.2
0.2
0.45
0.7
0.4
0.55
±5
10
500
pF
µA
V
Typ.†
M a x.
Units
One input a V
CC
–0.6V
Other inputs at V
CC
or GND
V
I
= V
CC
or GND
†
All typical values are measured at V
CC
= 3.3V, T
A
= 25°C
4
PS8671
03/21/03
PI74LVC74A
Fast CMOS 3.3V Dual Positive-Edge-Triggered
D-Type Flip-Flops with Clear & Preset
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Switching Characteristics
(Over recommended operating free-air temperature range,unless otherwise noted, see Figures 1 through 3)
Parame te rs
f
max
t
pd
tsk(o)
§
CLK
PRE or CLR
Q or Q
From
(Input)
V
CC
= 1.8V ±0.15V V
CC
= 2.5V ±0.2V
To
(Output)
M in.
M a x.
M in.
M a x.
83
1
1
7.1
6.9
83
1
1
6
6.4
V
CC
= 2.7V
M in.
83
1
1
5.2
5.4
M a x.
V
CC
= 3.3V ±0.3V
M in.
100
1
1
4.4
4.6
1
ns
M a x.
Units
MHz
§
Skew between any two outputs of the same package switching in the same direction.
Operating Characteristics, T
A
= 25°C
Parame te r
C
pd
De s cription
Power Dissipation Capacitance per flip- flop
Te s t
Conditions
f = 10 MHz
V
CC
= 1.8V
Typ.
44
V
CC
= 2.5V
Typ.
52
V
CC
= 3.3V
Typ.
62
pF
Units
Timing Requirements
(Over Recommended Operating Free-Air Temperature Range, unless otherwise noted, see Figures 1 through 3.)
Parame te r
f
clock
t
w
De s cription
Clock frequency
Pulse
Duration
PRE or CLR low
CLK high or low
V
CC
= 1.8V
± 0.15V
M in.
M a x.
83
4.1
4.1
3.6
2.7
1
V
CC
= 2.5V
± 0.2V
M in.
M a x.
83
3.3
3.3
2.3
1.9
1
V
CC
= 2.7V
M in.
M a x.
83
3.3
3.3
3.4
2.2
1
V
CC
= 3.3V
± 0.3V
M in.
M a x.
100
3.3
3.3
3
2
0
Units
MHz
t
su
t
h
Setup time Data
before CLK
↑
PRE or CLR inactive
Hold time, data after CLK
↑
ns
5
PS8671
03/21/03
嵌入式系统
