PI7C9X118SL
PCI Express-to-PCI Bridge
Datasheet
January 2017
Revision 1.4
1545 Barber Lane Milpitas, CA 95035
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17-0012
PI7C9X118SL
PR
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Copyright © 2016, Diodes Incorporated
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PI7C9X118SL
Rev 1.4
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REVISION HISTORY
DATE
07/31/2011
09/05/2011
12/15/2011
05/28/2013
REVISION #
0.1
0.2
1.0
1.1
DESCRIPTION
Preliminary Datasheet
Updated Section 2.7 Power and Ground Pins (1.1V power supply to 1.0V)
PI7C9X118SL datasheet release
Remove Figure 8-2 Topology of internal clock generator and internal clock
buffering – external feedback mode
Remove Figure 8-4 Topology of external clock generator and internal clock
buffering – external feedback mode
Remove NC and pin 22 from Section 2.6 and added pin 22 to Section 2.7 under
pin name VSS
Updated Section 2.5 JTAG Boundary Scan Signals
Updated Logo
Updated Section 2.7 Power and Ground Pins
Updated Section 2.8 Pin Assignments
Updated Section 14.1 Absolute Maximum Ratings
Updated Section 14.2 DC Specifications
Added Section 14.4 Operating Ambient Temperature
07/24/2014
04/21/2016
01/18/2017
1.2
1.3
1.4
PREFACE
The datasheet of PI7C9X118SL will be enhanced periodically when updated information is available. The
technical information in this datasheet is subject to change without notice. This document describes the
functionalities of PI7C9X118SL (PCI Express Bridge) and provides technical information for designers to design
their hardware using PI7C9X118SL.
PI7C9X118SL
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January 2017
© Diodes Incorporated
PI7C9X118SL
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TABLE OF CONTENTS
1
INTRODUCTION ........................................................................................................................ 10
1.1
1.2
1.3
1.4
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3
3.1
3.2
4
4.1
4.2
5
5.1
5.2
6
6.1
6.2
6.3
INDUSTRY SPECIFICATION COMPLIANCE ................................................................... 10
GENERAL FEATURES ......................................................................................................... 11
PCI EXPRESS FEATURES ................................................................................................... 11
PCI FEATURES ..................................................................................................................... 11
SIGNAL TYPES ..................................................................................................................... 12
PCI EXPRESS SIGNALS ...................................................................................................... 12
PCI SIGNALS ........................................................................................................................ 12
MODE SELECT AND STRAPPING SIGNALS ................................................................... 14
JTAG BOUNDARY SCAN SIGNALS .................................................................................. 14
MISCELLANEOUS SIGNALS ............................................................................................. 14
POWER AND GROUND PINS ............................................................................................. 14
PIN ASSIGNMENTS ............................................................................................................. 16
FUNCTIONAL MODE SELECTION .................................................................................... 17
PIN STRAPPING ................................................................................................................... 17
TRANSPARENT MODE ....................................................................................................... 18
FORWARD BRDIGE ............................................................................................................. 18
TLP STRUCTURE ................................................................................................................. 20
VIRTUAL ISOCHRONOUS OPERATION .......................................................................... 20
CONFIGURATION REGISTER MAP .................................................................................. 21
PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ............................................ 23
PCI CONFIGURATION REGISTERS .................................................................................. 25
VENDOR ID – OFFSET 00h ................................................................................................................ 25
DEVICE ID – OFFSET 00h .................................................................................................................. 25
COMMAND REGISTER – OFFSET 04h .............................................................................................. 25
PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................... 26
REVISION ID REGISTER – OFFSET 08h ........................................................................................... 27
CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 27
CACHE LINE SIZE REGISTER – OFFSET 0Ch .................................................................................. 27
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 27
HEADER TYPE REGISTER – OFFSET 0Ch ........................................................................................ 27
RESERVED REGISTERS – OFFSET 10h TO 17h ................................................................................ 28
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 28
SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 28
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PIN DEFINITIONS ...................................................................................................................... 12
MODE SELECTION AND PIN STRAPPING.......................................................................... 17
TRANSPARENT AND FORWARD BRIDGING..................................................................... 18
PCI EXPRESS FUNCTIONAL OVERVIEW........................................................................... 20
CONFIGURATION REGISTER ACCESS............................................................................... 21
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
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6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.3.18
6.3.19
6.3.20
6.3.21
6.3.22
6.3.23
6.3.24
6.3.25
6.3.26
6.3.27
6.3.28
6.3.29
6.3.30
6.3.31
6.3.32
6.3.33
6.3.34
6.3.35
6.3.36
6.3.37
6.3.38
6.3.39
6.3.40
6.3.41
6.3.42
6.3.43
6.3.44
6.3.45
6.3.46
6.3.47
6.3.48
6.3.49
6.3.50
6.3.51
6.3.52
6.3.53
6.3.54
6.3.55
6.3.56
6.3.57
6.3.58
6.3.59
6.3.60
6.3.61
6.3.62
6.3.63
6.3.64
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 28
SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 28
I/O BASE REGISTER – OFFSET 1Ch .................................................................................................. 28
I/O LIMIT REGISTER – OFFSET 1Ch ................................................................................................. 28
SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 28
MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 29
MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 29
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ......................................................... 30
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ........................................................ 30
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 30
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch ............................................... 30
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h ......................................................................... 30
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 30
CAPABILITY POINTER – OFFSET 34h .............................................................................................. 30
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 31
INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................... 31
INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 31
BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 31
PCI DATA PREFETCHING CONTROL REGISTER – OFFSET 40h .................................................. 32
CHIP CONTROL 0 REGISTER – OFFSET 40h ................................................................................... 34
RESERVED REGISTER – OFFSET 44h............................................................................................... 35
ARBITER ENABLE REGISTER – OFFSET 48h ................................................................................... 35
ARBITER MODE REGISTER – OFFSET 48h ...................................................................................... 35
ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 36
RESERVED REGISTERS – OFFSET 4Ch ............................................................................................ 36
MEMORY READSMART BASE LOWER 32-Bit REGISTER 1 – OFFSET 50h.................................... 37
MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h .................................... 37
MEMORY READSMART RANGE CONTROL REGISTER 1 – OFFSET 58h ...................................... 37
MEMORY READSMART BASE LOWER 32-Bit REGISTER 2 – OFFSET 5Ch ................................... 37
MEMORY READSMART BASE UPPER 32-Bit REGISTER 2 – OFFSET 60h .................................... 37
MEMORY READSMART RANGE SIZE REGISTER 2 – OFFSET 64h ................................................ 37
UPSTREAM MEMORY READ/WRITE CONTROL REGISTER – OFFSET 68h .................................. 38
PHY TRANSMIT/RECEIVE CONTROL REGISTER – OFFSET 6Ch .................................................. 38
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h ........................................... 39
RESERVED REGISTER – OFFSET 74h............................................................................................... 40
GPIO DATA AND CONTROL REGISTER – OFFSET 78h .................................................................. 40
RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 40
PCI-X CAPABILITY ID REGISTER – OFFSET 80h ............................................................................ 40
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 40
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h .................................................................. 40
PCI-X BRIDGE STATUS REGISTER – OFFSET 84h .......................................................................... 41
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 42
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 42
POWER MANAGEMENT ID REGISTER – OFFSET 90h .................................................................... 42
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 43
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 43
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 44
PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 44
SUBTRACTIVE DECODING PCI-TO-PCI BRIDGE ENABLE – OFFSET 98h .................................. 44
RESERVED REGISTERS – OFFSET 9Ch ............................................................................................ 45
CAPABILITY ID REGISTER – OFFSET A0h ....................................................................................... 45
NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 45
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PI7C9X118SL
Rev 1.4
17-0012
January 2017
© Diodes Incorporated
