PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
LVDS High-Speed Differential
Line Receivers
Features
•
Signaling Rates >400Mbps (200 MHz)
•
Single 3.3V Power Supply Design
•
Accepts ±350mV (typical) Differential Swing
•
Maximum Differential Skew of 0.35ns
•
Integrated 110-Ohm termination on PI90LVTxxxx
•
Maximum Propagation Delay of 4.7ns
•
Low Voltage TTL (LVTTL) Outputs
•
Industrial Temperature Operating Range: -40°C to 85°C
•
Open, Short, and Terminated Fail Safe
•
Meets or Exceeds ANSI/TIA/EIA-644 LVDS Standard
• Packaging (Pb-free & Green available):
-16-Pin TSSOP (L )
-16-Pin SOIC (W)
-8-Pin SOIC (W)
-8-Pin MSOP (U)
Description
The PI90LV/LVT3486 and PI90LV/LVT9637 are differential line
receivers that use low-voltage differential signaling (LVDS) to
support data rates in excess of 400 Mbps. These products are
designed for applications requiring high-speed, low-power con-
sumption and low noise generation.
A differential input signal (350mV) is translated by the device to 3V
CMOS output level.
Applications
Applications include point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately
100-ohms. The transmission media can be printed circuit board
traces, backplanes, or cables.
The PI90LV/LVT3486 and PI90LV/LVT9637, as well as companion
line drivers PI90LV/LVB3487 and PI90LV/LVB9638 provide new
alternatives to RS-232, PECL, and ECL devices for high-speed,
point-to-point interface applications.
PI90LV/LVT3486
16-Pin
W, L
PI90LV/LVT9637
8-Pin
W,U
1
PS8667A
10/04/04
Note:
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Absolute Maximum Ratings
(see Note 1, Page 4)
Supply Voltage (V
CC
) ....................................... –0.3V to +4.0V
Input Voltage (R
IN+
, R
IN-
) ............................... –0.3V to +3.9V
Enable Input Voltage (EN) ...................... –0.3V to (V
CC
+0.3V)
Output Voltage (R
OUT
) .......................... –0.3V to (V
CC
+0.3V)
S Package .................................................................... 750mW
Derate S Package ................................8.2mW/°C above +25°C
Storage Temperature Range .......................... –65°C to +150°C
Lead Temperature Range Soldering (4s) ...................... +260°C
Maximum Junction Temperature .................................. +150°C
ESD Rating ...................................................................
≥
10kV
Function Tables
PI90LV/LVT3486
Enable
EN
H
H
H
L
H
Diffe re ntial Inputs
R
IN+
, R
IN–
V
ID
≥
100mV
–100mV < V
ID
< 100mV
V
ID
≤
–100mV
X
Open
Output
R
OUT
H
?
L
Z
H
PI90LV/LVT9637
Diffe re ntial Inputs
R
IN+
, R
IN–
V
ID
≥
100mV
–100mV < V
ID
< 100mV
V
ID
≤
–100mV
Open
Output
R
OUT
H
?
L
H
Recommended Operating Conditions
M in.
Supply Voltage (V
CC
)
Receiver Input Voltage
Operating Free Air
Temperature (T
A
)
+3.0
GND
–40
+25
Typ.
+3.3
M a x.
+3.6
+3.0
+85
Units
V
Pin Descriptions
°C
Name
R
OUT
R
IN+
R
IN–
GND
V
CC
De s cription
TTL/CMOS receiver output pins
Non- inverting receiver input pins
Inverting receiver input pins
Ground pin
Positive power supply pin, +3.3V ±10%
2
PS8667A
10/04/04
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 2)
Symbol
V
TH
V
TL
VCMR
I
IN
Parame te r
Differential Input High
Threshold
Differential Input Low
Threshold
Common- Mode Voltage
Range
Input Current
Conditions
Pin
M in.
Typ.
+20
M ax.
+100
Units
mV
Vcm = +1.2V
(12)
–100
V
ID
= 200mV peak- to- peak
(5)
V
IN
= +2.8V
V
IN
= 0V
V
IN
= +3.6V
R
IN+
,
R
IN-
0.1
–10
–10
–20
2.7
2.7
R
OUT
2.7
3.0
3.0
3.0
0.1
–15
–10
2.0
V
IN
= 0V or V
CC
, Other Input = V
CC
or GND
I
CL
= –18mA
EN = V
CC
or GND, Inputs Open
EN = 2.4V or 0.5V, Inputs Open
EN = GND, Inputs Open
V
CC
EN
GND
–20
–1. 5
±1
–0.8
10
10
7
5
PI90LVTxxxx
90
110
15
15
10
10
143
–48
±1
0.25
–12 0
+10
V
CC
0.8
+20
±1
±1
–20
2.6
+10
+10
+20
V
V
CC
= +3.6 or 0V
V
CC
= 0V
µA
V
OH
Output High Voltage
I
OH
= –0.4mA, V
ID
= +200mV
I
OH
= –0.4mA, Input terminated
I
OH
= –0.4mA, Input shorted
V
V
OL
I
OS
I
OZ
V
IH
V
IL
I
I
V
CL
I
CC
Output Low Voltage
Output Short Circuit Current
Output Three- State Current
Input High Voltage
Input Low Voltage
Input Current
Input Clamp Voltage
No Load Supply Current
Receivers Enabled
No Load Supply Current
Receivers Disabled
Input Capacitance
Termination Impedance
I
OL
= 2mA, V
ID
= –200mV
Enabled, Vout = 0V
(10)
Disabled, V
OUT
= 0V or V
CC
mA
µA
V
µA
V
mA
I
CCZ
C
W
R
TERM
pF
Ω
3
PS8667A
10/04/04
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Switching Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 3,4,7,8)
Symbol
t
PHLD
t
PLHD
t
SKD1
t
SKD2
t
SKD3
t
SKD4
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
f
MAX
Parame te r
Differential Propagation Delay High to Low (V
CM
= 1.23V)
Differential Propagation Delay Low to High (V
CM
= 1.23V)
Differential Pulse Skew | t
PHLD
- t
PLHD
|
(6)
Differential Channel- to- Channel Skew- same device
(7)
Differential Part- to- Part Skew
(8)
Differential Part- to- Part Skew
(9)
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Maximum Operating Frequency
(13)
Conditions
M in.
1.8
1.8
0
Typ.
M a x.
4.7
4.7
Units
0.1
0.1
0.5
0.5
1.0
1.5
C
L
= 10pF
V
ID
= 200mV
(Figures 1 & 2)
0
0.35
0.35
R
L
= 2k
Ω
C
L
= 10pF
(Figures 3 & 4)
All channels switching
8
6
11
11
250
1.2
1.2
12
12
17
17
ns
MHz
Notes:
1.
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
2.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless
otherwise specified.
3.
All typicals are given for: V
CC
= +3.3V, T
A
= +25°C.
4.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50Ω, t
R
and t
F
(0% to 100%)
≤ 3ns
for R
IN
.
5.
The VCMR range is reduced for larger V
ID
. Example : if V
ID
= 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs
shorted is valid over a common-mode range of 0V to 2.3V. A V
ID
up tp V
CC
- 0V may be applied to the R
IN+
/ R
IN-
inputs with the
Common-Mode voltage set to V
CC
/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to
400mV. Skew specifications apply for 200mV
≤
V
ID
≤
800mV over the common mode range.
6.
tskd1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
7.
t
SKD2
, Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the
same chip with any event on the inputs.
8.
t
SKD3
, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies to devices
at the same V
CC
,and within 5ºC of each other within the operating temperature range.
9.
t
SKD4
, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies
to devices over recommended operating temperature and voltage ranges, and across process distribution. tskd4 is defined as
IMax
- Mini
differential propagation delay.
10. Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at
a time, do not exceed maximum junction temperature specification.
11. C
L
includes probe and jig capacitance.
12. V
CC
is always higher than R
IN+
and R
IN-
voltage. R
IN-
and R
IN+
are allowed to have a voltage range -0.2V to V
CC
- V
ID
/2.
However, to be compliant with AC specifications, the common voltage range 0.1V to 2.3V.
13. fmax generator input conditions: t
R
= t
F
< 1ns, (0% to 100%), 50% duty cycle, differential (1.05V to1.35V peak to peak).
Output Criteria: duty cycle = 60%/40%, V
OL
(max 0.4V), V
OH
(min 2.7V), Load = 10pF (stray plus probes).
4
PS8667A
10/04/04
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV3486/PI90LVT3486
PI90LV9637/PI90LVT9637
LVDS High-Speed Differential Line Receivers
Parameter Measurement Information
RIN+
Generator
RIN–
R
CL
50Ω
50Ω
ROUT
Receiver Enabled
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
R
IN-
0V (Differential)
R
IN+
t
PLHD
80%
R
OUT
20%
t
TLH
t
THL
1.5V
t
PHLD
80%
1.5V
20%
V
ID =
200mV
+1.2V
+1.3V
+1.1V
V
OL
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
C
L
includes load and test jig capacitance.
S
1
= V
CC
for T
PZL
, and T
PLZ
measurements
S
1
= GND for t
PZH
and t
PHZ
measurements
V
CC
S
1
R
L
EN
Generator
50Ω
R
IN+
R
IN–
Device
Under
Test
C
L
R
OUT
Figure 3. Receiver Three-State Delay Test Circuit
5
PS8667A
10/04/04
