PI90SD1636C
SERDES Gigabit Ethernet Transceiver
Features
• IEEE 802.3z Gigabit Ethernet Compliant
• Supports 1.25 Gbps Using NRZ Coding over uncompensated
twin coax cable
• Fully integrated CMOS IC
• Low Power Consumption
• ESD rating >2000V (Human Body Model) or > 200V (Ma-
chine Model)
• 5-Volt Input Tolerance
• Pin-Compatible with Agilent HDMP1636A/HDMP- 1646A
and Vitesse VSC7123 transceivers (see Appendix A)
• Packaging (Pb-free & Green available):
- 64-pin LQFP (FC)
- 64-pin LQFP (FD)
Description
The PI90SD1636C is a single chip, Gigabit Ethernet transceiver.
It performs all the functions of the Physical Medium Attachment
(PMA) portion of the Physical layer, as specified by the IEEE
802.3z Gigabit Ethernet standard. These functions include parallel-
to-serial and serial-to-parallel conversion, clock generation, clock
data recovery, and word synchronization. In addition, an internal
loopback function is provided for system debugging.
The PI90SD1636C is ideal for Gigabit Ethernet, serial backplane
and proprietary point-to-point applications. The device sup-
ports 1000BASE-LX and 1000BASE-SX
fi
ber-optic media, and
1000BASE-CX copper media.
The transmitter section of the PI90SD1636C accepts 10-bit wide
parallel TTL data and converts it to a high speed serial data stream.
The parallel data is encoded in 8b/10b format. This incoming
parallel data is latched into an input register, and synchronized
on the rising edge of the 125 MHz reference clock supplied by
the user. A phase locked loop (PLL) locks to the 125 MHz clock.
The clock is then multiplied by 10 to produce a 1.25 GHz serial
clock that is used to provide the high speed serial data output. The
output is sent through a Pseudo Emitter Coupled Logic (PECL)
driver. This output connects directly to a copper cable in the case
of 1000BASE-CX medium, or to a
fi
ber optic module in the case
of 1000BASE-LX or 1000BASE SX
fi
ber optic medium.
The receiver section of the PI90SD1636C accepts a serial PECL-
compatible data stream at a 1.25 Gbps rate, recovers the original
10-bit wide parallel data format, and retimes the data. A PLL locks
onto the incoming serial data stream, and recovers the 1.25 GHz
high speed serial clock and data. This is accomplished by con-
tinually frequency locking onto the 125 MHz reference clock, and
by phase locking onto the incoming data stream. The serial data
is converted back to parallel data format. The ‘comma’ character
is used to establish byte alignment. Two 62.5 MHz clocks, 180
degrees out of phase, are recovered. These clocks are alternately
used to clock out the parallel data on the rising edge. This parallel
data is sent to the user in TTL-compatible form.
Applications
•
•
•
•
Gigabit Ethernet
Serial Backplane
Proprietary point-to-point applicaitons
Passive Optical Networks
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PI90SD1636C
SERDES Gigabit Ethernet Transceiver
Functional Block Diagram
EWRAP
10
TX<9:0>
Input Data
Latch
10
Shift Registers
DOUT+
DOUT-
TX_CLK
TX PLL Clock
Generator
62.5 MHz
RX_CLK<1>
RX_CLK<0>
62.5 MHz
÷
2
125 MHz
10
RX<9:0>
Output Latch
RX PLL Clock
Recovery
10
INPUT
SELECTOR
EN_CDET
COM_DET
FRAME
ENABLE
10
Shift
Registers
DIN+
DIN-
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PI90SD1636C
SERDES Gigabit Ethernet Transceiver
Pin Configuration
GND_RX_ESD
VCC_RX_ESD
VCC_RX_ESD
GND_TX_HS
VCC_TX_ECL
VCC_TX_HS
GND_RXA
GND_RXF
VCC_RXA
VCC_RXA
DOUT+
DOUT-
DIN+
DIN-
VCC_RXF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND_ESD
TX<0>
TX<1>
TX<2>
VCC_ESD
TX<3>
TX<4>
TX<5>
TX<6>
VCC_ESD
TX<7>
TX<8>
TX<9>
GND_ESD
GND_TXA
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
COM_DET
GND_RXT
RX<0>
RX<1>
RX<2>
VCC_RXT
RX<3>
RX<4>
RX<5>
RX<6>
VCC_RXT
RX<7>
RX<8>
RX<9>
GND_RXT
GND_RXD
GND_TXD
VCC_RXD
VCC_TXD
EWRAP
NC
RX_CLK<1>
RX_CLK<0>
VCC_RXD
EN_CDET
Table 1. I/O Type Definitions
Type
TTL_IN
TTL_OUT
HS_IN
HS_OUT
P
Definition
TTL Input
TTL Output
Hight-Speed Input
High-Speed Output
Power Ground
VCC_TXA
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SIG_DET
GND_RX
VCC_RX
TX_CLK
NC
NC
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11/08/07
PI90SD1636C
SERDES Gigabit Ethernet Transceiver
Table 2. Pin Description
Name
GND_ESD
VCC_ESD
TX<0>
TX<1>
TX<2>
TX<3>
TX<4>
TX<5>
TX<6>
TX<7>
TX<8>
TX<9>
GND_TXA
VCC_TXA
NC
EWRAP
VCC_TXD
GND_TXD
TX_CLK
VCC_RXD
GND_RXD
EN_CDET
Pin #
1, 14
5, 10
2
3
4
6
7
8
9
11
12
13
15
18
16, 17,27,
48, 49
19
20
21
22
23 28,
25
24
Type
P
Description
Power and ground pairs for pad ESD structure.
TTL_IN
0-bit parallel data input pins.
This data should be 10b/8b encoded. The least
significant bit is TX<0> and is transmitted
fi
rst.
P
NC
TTL_IN
Power and ground pair for TX PLL analog circuits.
No Connect
Wrap Enable.
This pin is active HIGH. When asserted, the high-speed serial data
are internally wrapped from the transmitter serial data output back to the receiver
data input. Also, when asserted, DOUT± are held static at logic 1. When deasserted,
DOUT± and .DIN± are active.
Power and ground pair for TX digital circuits.
Reference clock and transmit byte clock.
This is a 125 MHz system clock supplied
by the host system. On the positive edge of the clock, the input data, TX<9:0>, are
latched into the register. This clock is multiplied by 10 internally, to generate the
transmit serial bit clock.
Power and ground pair for digital circuits in the receiver portion.
Comma Detect Enable.
This pin is active HIGH. When asserted, the internal byte
alignment function is turned on, to allow the clock to synchronize with the comma
character (0011111XXX). When de-asserted, the function is disabled and will not align
the clock and data. In this mode COM_DET is set to LOW.
Signal Detect.
This pin is active HIGH. It indicates the loss of input signal on the
high-speed serial inputs, DIN±. SIG_DET is set to LOW when differential inputs are
less than 50 mV.
Power and ground pair for the clock signal of the receiver portion.
Receiver Byte Clocks.
Two 180 degrees out-of-phase 62.5 MHz clock signals that are
recovered by the receiver section. The received bytes are alternately clocked by the
rising edges of these signals. The rising edge of RX_CLK<1> aligns with a comma
character when detected.
P
TTL_IN
P
TTL_IN
TTL_
OUT
P
TTL_
OUT
SIG_DET
VCC_RX
GND_RX
RX_CLK<1>
RX_CLK<0>
26
29
32
30
31
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SERDES Gigabit Ethernet Transceiver
Table 2. Pin Description (Continued.)
Name
GND_RXT
VCC_RXT
RX < 9>
RX<8>
RX<7>
RX<6>
RX<5>
RX<4>
RX<3>
RX<2>
RX<1>
RX<0>
COM_DET
VCC_RXF
GND_RXF
DIN-
DIN+
VCC_RXESD
GND_RXESD
VCC_RXA
GND_RXA
VCC_TX_ECL
DOUT-
DOUT+
VCC_TX_HS
GND_TX_HS
Pin#
33 46,
37, 42
34
35
36
37
38
39
40
41
43
44
45
47
50
51
52
54
53,55
56
57, 59
58
60
61
62
63
64
P
P
P
HS_OUT
P
P
Type
Description
Power and ground pairs for ESD structure.
TT L _ OU T
Received Parallel Data Output.
RX<0> is the least significant bit and is
received
fi
rst. When DIN± lose input data, all RX pins will be held HIGH.
TTL_OUT
P
HS_IN
Comma detect.
This pin is active HIGH. When asserted, it indicates the
detection of comma character (0011111XXX). It is active only when EN_CEDT
is enabled.
Power and ground pair for the front-end of the receiver section.
High-speed serial data input.
Serial data input is received when
EWRAP is disabled.
Power and ground pair for ESD structure.
Power and ground pair for analog circuits of the receiver section.
Power supply to line driver circuits. Ground supply is from pin 64.
High-speed serial data output.
These pins are active when EWRAP is disabled
and are held static at logic 1 when EWRAP is enable.
Power and ground pair for high-speed transmit logic in the parallel-to-serial
section.
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