PIC12F629/675/PIC16F630/676
PIC12F629/675/PIC16F630/676 Memory Programming
This document includes the
programming specifications for the
following devices:
• PIC12F629
• PIC12F675
• PIC16F630
• PIC16F676
1.1
Hardware Requirements
The PIC12F629/675/PIC16F630/676 requires one
power supply for V
DD
(5.0V) and one for V
PP
(12V).
1.2
Programming Mode
1.0
PROGRAMMING THE
PIC12F629/675/PIC16F630/676
The Programming mode for the PIC12F629/675/
PIC16F630/676 allows programming of user program
memory, data memory, special locations used for ID
and the Configuration Word register.
The PIC12F629/675/PIC16F630/676 is programmed
using a serial method. The Serial mode will allow the
PIC12F629/675/PIC16F630/676 to be programmed
while in the user’s system. This allows for increased
design flexibility. This programming specification
applies to PIC12F629/675/PIC16F630/676 devices in
all packages.
FIGURE 1-1:
PDIP, SOIC
8-PIN DIAGRAMS FOR PIC12F629/675
V
DD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/V
PP
1
PIC12F629
2
3
4
8
7
6
5
V
SS
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/V
PP
PIC12F675
V
DD
1
2
3
4
8
7
6
5
V
SS
GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/V
REF
/ICSPCLK
GP2/AN2/T0CKI/INT/COUT
DFN, DFN-S
V
DD
GP5/TICKI/OSC1/CLKIN
GP4/TIG/OSC2/CLKOUT
GP3/MCLR/V
DD
1
2
PIC12F629
3
4
6
5
8
7
V
SS
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
V
DD
GP5/TICKI/OSC1/CLKIN
GP4/AN4/TIG/OSC2/CLKOUT
GP3/MCLR/V
DD
1
2
PIC12F675
3
4
8
7
6
5
V
SS
GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/ICSPCLK
GP2/AN2/T0CKI/INT/COUT
©
2005 Microchip Technology Inc.
DS41191D-page 1
PIC12F629/675/PIC16F630/676
FIGURE 1-2:
14-PIN DIAGRAMS FOR PIC16F630/676
PDIP, SOIC, TSSOP
V
DD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/CLKOUT
RA3/MCLR/V
PP
RC5
RC4
RC3
1
2
PIC16F630
3
4
5
6
7
14
13
12
11
10
9
8
V
SS
RA0/CIN+/ICSPDAT
RA1/CIN-/ICSPCLK
RA2/COUT/T0CKI/INT
RC0
RC1
RC2
V
DD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/AN3/CLKOUT
RA3/MCLR/V
PP
RC5
RC4
RC3/AN7
1
2
PIC16F676
3
4
5
6
7
14
13
12
11
10
9
8
V
SS
RA0/AN0/CIN+/ICSPDAT
RA1/AN1/CIN-/V
REF
/ICSPCLK
RA2/AN2/COUT/T0CKI/INT
RC0/AN4
RC1/AN5
RC2/AN6
QFN
V
DD
V
SS
13
12
11
10
9
5
6
7
8
NC
15
NC
14
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/CLKOUT
RA3/MCLR/V
PP
RC5
16
1
2
3
4
PIC16F630
RA0/C1IN+/ICSPDAT
RA1/CIN-/V
REF
/ICSPCLK
RA2/COUT/T0CKI/INT
RC0
RC4
RC3
RC2
RC1
V
DD
16
15
14
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/CLKOUT
RA3/MCLR/V
PP
RC5
13
V
SS
12
11
10
9
NC
NC
1
2
3
4
5
6
7
PIC16F676
RA0/AN0/C1IN+/ICSPDAT
RA1/AN1/CIN-/V
REF
/ICSPCLK
RA2/AN2/COUT/T0CKI/INT
RC0/AN4
RC4
RC3/AN7
RC2/AN6
RC1/AN5
8
DS41191D-page 2
©
2005 Microchip Technology Inc.
PIC12F629/675/PIC16F630/676
FIGURE 1-3:
SSOP
V
DD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/V
PP
RFXTAL
RFEN
CLKOUT
PS
V
DDRF
V
SSRF
•1
2
rfPIC12F675F/H/K
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
SS
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
FSK
OUT
DATA
FSK
DATA
ASK
LF
V
SSRF
ANT
20-PIN DIAGRAM FOR rfPIC12F675F/H/K
TABLE 1-1:
Pin Name
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12F629/675/PIC16F630/676
During Programming
Function
Pin Type
I
I/O
P
(1)
I
I/O
P
P
Pin Description
Clock Input – Schmitt Trigger Input (PIC12F629/675 only)
Data Input/Output – TTL Input (PIC12F629/675 only)
Program Mode Select
Clock Input – Schmitt Trigger Input (PIC16F630/676 only)
Data Input/Output – TTL Input (PIC16F630/676 only)
Power Supply
Ground
GP1
GP0
MCLR
RA1
RA0
V
DD
V
SS
CLOCK
DATA
Programming Mode
CLOCK
DATA
V
DD
V
SS
Legend:
I = Input, O = Output, P = Power
Note 1:
In the PIC12F629/675/PIC16F630/676, the programming high voltage is internally generated. To activate
the Programming mode, high voltage needs to be applied to the MCLR input. Since the MCLR is used for
a level source, the MCLR does not draw any significant current.
©
2005 Microchip Technology Inc.
DS41191D-page 3
PIC12F629/675/PIC16F630/676
2.0
2.1
PROGRAM MODE ENTRY
User Program Memory Map
2.2
ID Locations
The user memory space extends from 0x0000-0x1FFF.
In Programming mode, the program memory space
extends from 0x0000-0x3FFF, the first half (0x0000-
0x1FFF) is user program memory and the second half
(0x2000-0x3FFF) is configuration memory. The PC will
increment from 0x0000-0x1FFF and wrap to 0x000,
0x2000-0x3FFF and wrap around to 0x2000 (not to
0x0000). Once in configuration memory, the highest bit
of the PC remains a ‘1’, thus always pointing to the
configuration memory. The only way to point to the user
program memory is to reset the part and re-enter
Program/Verify mode as described in
Section 2.3
“Program/Verify Mode”.
In the configuration memory space, 0x2000-0x201F are
physically implemented. However, only locations 0x2000-
0x2003 and 0x2007 are available. Other locations are
reserved.
A user may store identification information (ID) in four ID
locations. The ID locations are mapped in [0x2000:
0x2003]. It is recommended that the user use only the
seven Least Significant bits (LSb) of each ID location.
Locations read out normally, even after code protection.
The ID locations read out in an unscrambled fashion
after code protection is enabled. It is recommended that
ID location is written as “xx
xxxx xbbb bbbb”
where
‘bbb
bbbb’
is ID information.
The 14 bits may be programmed, but only the LSbs are
displayed by MPLAB
®
IDE.
xxxx’s
are “don’t care” bits
as they won’t be read by MPLAB
®
IDE.
FIGURE 2-1:
PROGRAM MEMORY MAPPING
1 KW
Implemented
03FE
03FF Implemented
400
03FF
OSCCAL
Maps to
0-3FF
2000
ID Location
2001
ID Location
2002
ID Location
2003
ID Location
2004
Reserved
2005
Reserved
2006
Reserved
2007
Configuration Word
1FFF
2000
2008
201F
Implemented
Reserved
Maps to
2000-201F
3FFF
DS41191D-page 4
©
2005 Microchip Technology Inc.
PIC12F629/675/PIC16F630/676
2.3
Program/Verify Mode
The Program/Verify mode is entered by holding pins clock
and data low while raising MCLR pin from V
IL
to V
IHH
(high voltage). Apply V
DD
and data. Once in this mode,
the user program memory, data memory and the configu-
ration memory can be accessed and programmed in
serial fashion. Clock is Schmitt Trigger and data is TTL
input in this mode. GP4 (PIC12F629/675) or RA4
(PIC16F630/676) is tri-state, regardless of use setting.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at V
IL
). This means
that all I/O’s are in the Reset state (high-impedance
inputs).
A device Reset will clear the PC and set the address to
‘0’. The Increment Address command will increment
the PC. The Load Configuration command will set the
PC to 0x2000. The available commands are shown in
Table 2-1.
2.3.1
SERIAL PROGRAM/VERIFY
OPERATION
FIGURE 2-2:
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
T
PPDP
T
HLD
0
The clock pin is used as a clock input pin and the data
pin is used for entering command bits and data input/out-
put during serial operation. To input a command, the
clock pin (CLOCK) is cycled six times. Each command
bit is latched on the falling edge of the clock with the LSb
of the command being input first. The data on pin DATA
is required to have a minimum setup and hold time (see
Table 5-1), with respect to the falling edge of the clock.
Commands that have data associated with them (Read
and Load) are specified to have a minimum delay of 1
μs
between the command and the data. After this delay, the
clock pin is cycled 16 times with the first cycle being a
Start bit and the last cycle being a Stop bit. Data is also
input and output LSb first.
Therefore, during a read operation, the LSb will be
transmitted onto pin DATA on the rising edge of the
second cycle. During a load operation, the LSb will be
latched on the falling edge of the second cycle. A
minimum 1
μs
delay is also specified between
consecutive commands.
All commands are transmitted LSb first. Data words are
also transmitted LSb first. The data is transmitted on
the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1
μs
is required between a command and a data word
(or another command).
The commands that are available are described in
Table 2-1.
V
PP
V
DD
DATA
CLOCK
SDATA = Input
The normal sequence for programming is to use the
Load Data command to set a value to be written at the
selected address. Issue the Begin Programming
command followed by a Read Data command to verify
and then increment the address.
TABLE 2-1:
COMMAND MAPPING FOR PIC12F629/675/PIC16F630/676
Command
Mapping (MSb … LSb)
X
X
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
0
1
0
X
X
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
1
Internally Timed
Internally Timed
Internally Timed
Externally Timed
Data
0,
data (14),
0
0,
data (14),
0
0,
data (8), zero (6),
0
0,
data (14),
0
0,
data (8), zero (6),
0
Load Configuration
Load Data for Program Memory
Load Data for Data Memory
Read Data from Program Memory
Read Data from Data Memory
Increment Address
Begin Programming
Begin Programming
End Programming
Bulk Erase Program Memory
Bulk Erase Data Memory
©
2005 Microchip Technology Inc.
DS41191D-page 5
