PIC12F609/12F615/12F617/16F610/16F616 AND
PIC12HV609/12HV615/16HV610/16HV616
Flash Memory Programming Specification
1.0
DEVICE OVERVIEW
2.1
Hardware Requirements
This
document
includes
the
programming
specifications for the following devices:
• PIC12F615
• PIC12F609
• PIC12F617
• PIC16F616
• PIC16F610
• PIC12HV615
• PIC12HV609
• PIC16HV616
• PIC16HV610
These devices require one power supply for V
DD
, see
Table 7-1 V
DD
, and one for V
PP
, see Table 7-1 V
IHH
.
2.2
Program/Verify Mode
The Program/Verify mode for these devices allows pro-
gramming of user program memory, user ID locations,
Calibration Word and the Configuration Word.
Note 1:
All references to the PIC12F615 parts
refer to the PIC12HV615 parts as well
(unless otherwise specified).
2:
All references to the PIC16F616 parts
refer to the PIC16HV616 as well (unless
otherwise specified).
3:
All references to the PIC12F609 parts
refer to the PIC12HV609 as well (unless
otherwise specified).
4:
All references to the PIC16F610 parts
refer to the PIC16HV610 as well (unless
otherwise specified).
5:
Any references in this programming
specification to PORTA and RAn refer to
GPIO and GPn, respectively.
2.0
PROGRAMMING THE
PIC12F609/12F615/12F617/
16F610/16F616 AND
PIC12HV609/12HV615/16HV610/
16HV616 DEVICES
The PIC12F609/12F615/12F617/16F610/16F616 and
PIC12HV609/12HV615/16HV610/16HV616 devices are
programmed using a serial method. The Serial mode will
allow these devices to be programmed while in the user’s
system. These programming specifications apply to all of
the above devices in all packages.
2010 Microchip Technology Inc.
DS41284E-page 1
PIC12F609/12F615/12F617/16F610/16F616 AND PIC12HV609/12HV615/16HV610/16HV616
FIGURE 2-1:
8-PIN, 14-PIN, AND 16-PIN PROGRAMMING PINS DIAGRAM FOR PIC12F609/
12F615/12F617/16F610/16F616
(1)
V
DD
GP5
GP4
GP3/MCLR/V
PP
1
2
3
4
8
7
6
5
V
SS
GP0/ICSPDAT
GP1/ICSPCLK
GP2
8-Pin PDIP, SOIC, MSOP, DFN
14-Pin PDIP, SOIC, TSSOP
V
DD
RA5
RA4
RA3/MCLR/V
PP
RC5
RC4
RC3
1
2
3
4
5
6
7
PIC16F616/610
PIC12F615/609
PIC12F617
14
13
12
11
10
9
8
V
SS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
V
DD
16-Pin QFN
16
6
PIC16F616/HV616
15
14
1
2
3
4
5
PIC16F610/HV610
RA5
RA4
RA3/MCLR/V
PP
RC5
13
V
SS
NC
NC
12
11
10
9
8
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC4
RC3
RC2
7
Note
1:
Please see specific data sheets for alternate pin functionality.
TABLE 2-1:
PIN DESCRIPTIONS IN PROGRAM/VERIFY MODE: PIC12F609/12F615/12F617/
16F610/16F616 AND PIC12HV609/12HV615/16HV610/16HV616
During Programming
Function
ICSPCLK
ICSPDAT
Program/Verify mode
V
DD
V
SS
Pin Type
I
I/O
P
(1)
P
P
Pin Description
Clock input – Schmitt Trigger input
Data input/output – Schmitt Trigger input
Program Mode Select
Power Supply
Ground
Pin Name
GP1/RA1
GP0/RA0
MCLR
V
DD
V
SS
Legend:
I = Input, O = Output, P = Power
Note 1:
In the PIC12F609/12F615/12F617/16F610/16F616 and PIC12HV609/12HV615/16HV610/16HV616, the
programming high voltage is internally generated. To activate the Program/Verify mode, voltage of V
IHH
and a current of I
IHH
(see Table 7-1) needs to be applied to MCLR input.
RC1
DS41284E-page 2
2010 Microchip Technology Inc.
PIC12F609/12F615/12F617/16F610/16F616 AND PIC12HV609/12HV615/16HV610/16HV616
3.0
3.1
MEMORY DESCRIPTION
Program Memory Map
3.3
Calibration Word
The user memory space extends from 0x0000 to
0x1FFF. In Program/Verify mode, the program memory
space extends from 0x0000 to 0x3FFF, with the first
half (0x0000-0x1FFF) being user program memory and
the second half (0x2000-0x3FFF) being configuration
memory. The Program Counter (PC) will increment
from 0x0000 to 0x1FFF and wrap to 0x0000. If the PC
is between 0x2000 to 0x3FFF it will wrap around to
0x2000 (not to 0x0000). Once in configuration memory,
the highest bit of the PC stays a ‘1’, thus always point-
ing to the configuration memory. The only way to point
to user program memory is to reset the part and re-
enter Program/Verify mode as described in
Section 4.0 “Program/Verify Mode”.
For all of the devices covered in this document, the
configuration memory space, 0x2000 to 0x2008, is
physically implemented. However, only locations
0x2000 to 0x2003, 0x2007 and 0x2008 are available.
Other locations are reserved.
For all of the devices covered in this document, the
4/8 MHz Internal Oscillator (INTOSC) module is fac-
tory calibrated. This value is stored in the Calibration
Word (0x2008). See the applicable device data sheet
for more information.
The Calibration Word does not necessarily participate
in the erase operation unless a specific procedure is
executed. Therefore, the device can be erased without
affecting the Calibration Word. This simplifies the erase
procedure since these values do not need to be read
and restored after the device is erased.
3.2
User ID Locations
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped in 0x2000 to 0x2003. It is recommended that
the user use only the seven Least Significant bits
(LSbs) of each user ID location. The user ID locations
read out normally, even after code protection is
enabled. It is recommended that ID locations are writ-
ten as ‘xx
xxxx xbbb bbbb’
where ‘bbb
bbbb’
is the
user ID information.
The 14 bits may be programmed, but only the 7 LSbs
are read and displayed by MPLAB
®
IDE.
2010 Microchip Technology Inc.
DS41284E-page 3
PIC12F609/12F615/12F617/16F610/16F616 AND PIC12HV609/12HV615/16HV610/16HV616
FIGURE 3-1:
PIC12F615/HV615, PIC12F609/HV609, PIC16F610/HV610 PROGRAM MEMORY
MAPPING
1 KW
Implemented
03FF
Program Memory
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009-203F
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word
Calibration Word
Reserved
3FFF
Maps to
2000-203F
Configuration Memory
1FFF
2000
2040
Implemented
Maps to
0-3FF
DS41284E-page 4
2010 Microchip Technology Inc.
PIC12F609/12F615/12F617/16F610/16F616 AND PIC12HV609/12HV615/16HV610/16HV616
FIGURE 3-2:
PIC12F617/PIC16F616/HV616 PROGRAM MEMORY MAPPING
2 KW
Implemented
07FF
Program Memory
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009-203F
2009-206F
(1)
Note 1:
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word
Calibration Word
Reserved
3FFF
Maps to
2000-203F
2000-206F
(1)
Configuration Memory
1FFF
2000
2040
2070
(1)
Implemented
Maps to
0-7FF
Applies to the PIC12F617 only.
2010 Microchip Technology Inc.
DS41284E-page 5
