PIC18F2XK20/4XK20
Flash Memory Programming Specification
1.0
DEVICE OVERVIEW
2.1
Hardware Requirements
This
document
includes
the
programming
specifications for the following devices:
•
•
•
•
•
•
•
•
PIC18F23K20
PIC18F24K20
PIC18F25K20
PIC18F26K20
PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20
In High-Voltage ICSP mode, the PIC18F2XK20/4XK20
devices require two programmable power supplies:
one for V
DD
and one for MCLR/V
PP
/RE3. Both supplies
should have a minimum resolution of 0.25V. Refer to
Section 6.0
“AC/DC
Characteristics
Timing
Requirements for Program/Verify Test Mode”
for
additional hardware parameters.
2.1.1
LOW-VOLTAGE ICSP
PROGRAMMING
2.0
PROGRAMMING OVERVIEW
The PIC18F2XK20/4XK20 devices can be pro-
grammed using either the high-voltage In-Circuit Serial
Programming™ (ICSP™) method or the low-voltage
ICSP method. Both methods can be done with the
device in the users’ system. The low-voltage ICSP
method is slightly different than the high-voltage
method and these differences are noted where applica-
ble. This programming specification applies to the
PIC18F2XK20/4XK20 devices in all package types.
In Low-Voltage ICSP mode, the PIC18F2XK20/4XK20
devices can be programmed using a single V
DD
source
in the operating range. The MCLR/V
PP
/RE3 does not
have to be brought to a different voltage, but can
instead be left at the normal operating voltage. Refer to
Section 6.0
“AC/DC
Characteristics
Timing
Requirements for Program/Verify Test Mode”
for
additional hardware parameters.
2.2
Pin Diagrams
The pin diagrams for the PIC18F2XK20/4XK20 family
are shown in Figure 2-3 and Figure 2-4.
TABLE 2-1:
Pin Name
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XK20/4XK20
During Programming
Pin Name
Pin Type
P
P
P
I
I
I/O
Programming Enable
Power Supply
Ground
Low-Voltage ICSP™ input when LVP Configuration bit equals ‘1’
(1)
Serial Clock
Serial Data
Pin Description
MCLR/V
PP
/RE3
V
DD
(2)
V
SS
(2)
RB5
RB6
RB7
V
PP
V
DD
V
SS
PGM
PGC
PGD
Legend:
I = Input, O = Output, P = Power
Note 1:
See Figure 5-1 for more information.
2:
All power supply (V
DD
) and ground (V
SS
) pins must be connected.
©
2009 Microchip Technology Inc.
Advance Information
DS41297F-page 1
PIC18F2XK20/4XK20
FIGURE 2-1:
28-PIN SDIP, SSOP AND SOIC PIN DIAGRAMS
SDIP, SSOP, SOIC (300 MIL)
MCLR/V
PP
/RE3
RA0
RA1
RA2
RA3
RA4
RA5
V
SS
OSC1
OSC2
RC0
RC1
RC2
RC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
RC6
RC5
RC4
Note:
The following devices are included in 28-pin SDIP, SSOP and SOIC parts: PIC18F23K20, PIC18F24K20,
PIC18F25K20, PIC18F26K20.
FIGURE 2-2:
28-Pin QFN
28-PIN QFN PIN DIAGRAMS
MCLR/V
PP
/RE3
RB7/PGD
RB6/PGC
RB5/PGM
RB4
21
20
19
18
17
16
15
28 27 26 25 24 23 22
RA2
RA3
RA4
RA5
V
SS
OSC1
OSC2
1
2
3
4
5
6
7
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
8 9 10 11 12 13 14
Note:
The following devices are included in 28-pin QFN parts: PIC18F23K20, PIC18F24K20, PIC18F25K20,
PIC18F26K20.
DS41297F-page 2
Advance Information
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RA1
RA0
PIC18F2XK20
PIC18F2XK20
©
2009 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 2-3:
40-PIN PDIP PIN DIAGRAMS
40-PIN PDIP (600 MIL)
MCLR/V
PP
/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
V
DD
V
SS
OSC1
OSC2
RC0
RC1
RC2
RC3
RD0
RD1
Note:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3
RB2
RB1
RB0
V
DD
V
SS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
The following devices are included in 40-pin PDIP parts: PIC18F43K20, PIC18F44K20, PIC18F45K20,
PIC18F46K20.
FIGURE 2-4:
44-PIN TQFP
44-PIN TQFP PIN DIAGRAMS
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
PIC18F4XK20
Note:
The following devices are included in 44-pin TQFP parts: PIC18F43K20, PIC18F44K20, PIC18F45K20,
PIC18F46K20.
©
2009 Microchip Technology Inc.
Advance Information
NC
NC
RB4
RB5/PGM
RB6/PGC
RB7/PGD
MCLR/V
PP
/RE3
RA0
RA1
RA2
RA3
12
13
14
15
16
17
18
19
20
21
22
RC7
RD4
RD5
RD6
RD7
V
SS
V
DD
RB0
RB1
RB2
RB3
1
2
3
4
5
PIC18F4XK20
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
NC
RC0
OSC2
OSC1
V
SS
V
DD
RE2
RE1
RE0
RA5
RA4
DS41297F-page 3
PIC18F2XK20/4XK20
FIGURE 2-5:
44-PIN QFN
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
44
43
42
41
40
39
38
37
36
35
34
44-PIN QFN PIN DIAGRAMS
Note:
The following devices are included in 44-pin QFN parts: PIC18F43K20, PIC18F44K20, PIC18F45K20,
PIC18F46K20.
DS41297F-page 4
Advance Information
RB3
NC
RB4
RB5/PGM
RB6/PGC
RB7/PGD
MCLR/V
PP
/RE3
RA0
RA1
RA2
RA3
12
13
14
15
16
17
18
19
20
21
22
RC7
RD4
RD5
RD6
RD7
V
SS
V
DD
V
DD
RB0
RB1
RB2
1
2
3
4
5
PIC18F4XK20
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
OSC2
OSC1
V
SS
V
SS
V
DD
V
DD
RE2
RE1
RE0
RA5
RA4
©
2009 Microchip Technology Inc.
PIC18F2XK20/4XK20
2.3
Memory Maps
TABLE 2-2:
Device
PIC18F23K20
PIC18F43K20
For the PIC18FX3K20 devices, the code memory
space extends from 0000h to 01FFFh (8 Kbytes) in two
4-Kbyte blocks. Addresses 0000h through 01FFh,
however, define a “Boot Block” region that is treated
separately from Block 0. All of these blocks define code
protection boundaries within the code memory space.
IMPLEMENTATION OF CODE
MEMORY
Code Memory Size (Bytes)
000000h-001FFFh (8K)
FIGURE 2-6:
000000h
MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX3K20 DEVICES
Code Memory
01FFFFh
MEMORY SIZE/DEVICE
8 Kbytes
(PIC18FX3K20)
Boot Block
Unimplemented
Read as ‘0’
Address
Range
000000h
0001FFh
000200h
Block 0
000FFFh
001000h
Block 1
001FFFh
002000h
200000h
Unimplemented
Read ‘0’s
Configuration
and ID
Space
01FFFFh
3FFFFFh
Note:
Sizes of memory areas are not to scale.
©
2009 Microchip Technology Inc.
Advance Information
DS41297F-page 5
WindowsCE
