PIC18FXX80/XX85
Flash Microcontroller Programming Specification
1.0
DEVICE OVERVIEW
2.1
2.1.1
Hardware Requirements
HIGH-VOLTAGE ICSP
PROGRAMMING
This
document
includes
the
programming
specifications for the following devices:
• PIC18F6585
• PIC18F8585
• PIC18F6680
• PIC18F8680
2.0
PROGRAMMING OVERVIEW
PIC18FXX80/XX85 devices can be programmed using
either the high-voltage In-Circuit Serial Programming
TM
(ICSP
TM
) method, or the low-voltage ICSP method.
Both of these programming methods can be done with
the device in the user’s system. The low-voltage ICSP
method is slightly different than the high-voltage
method, and these differences are noted where appli-
cable. This programming specification applies to
PIC18FXX80/XX85 devices in all package types.
In High-Voltage ICSP mode, these devices require two
programmable power supplies: one for V
DD
and one for
MCLR/V
PP
. Both supplies should have a minimum
resolution of 0.25V. Refer to
Section 6.0 “AC/DC
Characteristics Timing Requirements for Program/
Verify Test Mode”
for additional hardware parameters.
2.1.2
LOW-VOLTAGE ICSP
PROGRAMMING
In Low-Voltage ICSP mode, these devices can be pro-
grammed using a V
DD
source in the operating range.
This only means that MCLR/V
PP
does not have to be
brought to a different voltage but can instead be left at the
normal operating voltage. Refer to
Section 6.0 “AC/DC
Characteristics Timing Requirements for Program/
Verify Test Mode”
for additional hardware parameters.
2.2
Pin Diagrams
The pin diagrams for the PIC18FXX80/XX85 family are
shown in Figure 2-1, Figure 2-2 and Figure 2-3. The
pin descriptions of these diagrams do not represent the
complete functionality of the device types. Users
should refer to the appropriate device data sheet for
complete pin descriptions.
TABLE 2-1:
Pin Name
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX80/XX85
During Programming
Pin Name
Pin Type
P
P
P
P
P
I
I
I/O
I
Programming Enable
Power Supply
Ground
Analog Power Supply
Analog Ground
Low-Voltage ICSP™ Input when LVP Configuration bit equals ‘1’
(1)
Serial Clock
Serial Data
Oscillator Input (needs to be pulled high during programming.)
Pin Description
MCLR/V
PP
/RA5
V
DD
(2)
V
SS
(2)
AV
DD
(2)
AV
SS
(2)
RB5
RB6
RB7
OSC1
V
PP
V
DD
V
SS
AV
DD
AV
SS
PGM
PGC
PGD
OSC1
Legend:
I = Input, O = Output, P = Power
Note 1:
See
Section 5.3 “Low-Voltage Programming (LVP) Bit”
for more detail.
2:
All power supplies and ground must be connected.
2010 Microchip Technology Inc.
DS39606E-page 1
PIC18FXX80/XX85
FIGURE 2-1:
TQFP
RE7/CCP2
(1)
64-PIN TQFP PACKAGE DIAGRAM FOR PIC18F6X8X
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RD7/PSP7
RE5/P1C
RE6/P1B
RE2/CS
RE3
RE4
V
DD
V
SS
RE1/WR
RE0/RD
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG5/MCLR/V
PP
RG4/P1D
V
SS
V
DD
RF7/SS
RF6/AN11/C1IN-
RF5/AN10/C1IN+/CV
REF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
V
SS
OSC2/CLKO/RA6
OSC1/CLKI
V
DD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
PIC18F6X8X
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF1/AN6/C2OUT
RF0/AN5
RA2/AN2/V
REF
-
RA4/T0CKI
RC1/T1OSI/CCP2
(1)
RC0/T1OSO/T13CKI
AV
SS
RA3/AN3/V
REF
+
RA5/AN4/LVDIN
Note 1:
CCP2 pin placement depends on the Processor mode settings.
RC7/RX/DT
RC6/TX/CK
RA1/AN1
RA0/AN0
AV
DD
V
DD
V
SS
DS39606E-page 2
2010 Microchip Technology Inc.
PIC18FXX80/XX85
FIGURE 2-2:
PLCC
RE2/CS
RE3
RE4
RE5/P1C
RE6/P1B
RE7/CCP2
(1)
RD0/PSP0
V
DD
N/C
V
SS
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
RE1/WR
RE0/RD
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG5/MCLR/V
PP
RG4/P1D
N/C
V
SS
V
DD
RF7/SS
RF6/AN11/C1IN-
RF5/AN10/C1IN+/CV
REF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
V
SS
N/C
OSC2/CLKO/RA6
OSC1/CLKI
V
DD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
Top View
68-PIN PLCC PACKAGE DIAGRAM FOR PIC18F6X8X
PIC18F6X8X
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
RF1/AN6/C2OUT
RF0/AN5
AV
DD
AV
SS
RA3/AN3/V
REF
+
RA2/AN2/V
REF
-
RA1/AN1
RA0/AN0
N/C
V
SS
Note 1:
2010 Microchip Technology Inc.
CCP2 pin placement depends on the Processor mode settings.
V
DD
RA5/AN4/LVDIN
RA4/T0CKI
RC1/T1OSI/CCP2
(1)
RC0/T1OSO/T13CKI
RC6/TX/CK
RC7/RX/DT
DS39606E-page 3
PIC18FXX80/XX85
FIGURE 2-3:
80-PIN TQFP PACKAGE DIAGRAM FOR PIC18F8X8X
TQFP
RE7/CCP2
(2)
/AD15
RD0/PSP0
(1)
/AD0
RD1/PSP1
(1)
/AD1
RD2/PSP2
(1)
/AD2
RD3/PSP3
(1)
/AD3
RD4/PSP4
(1)
/AD4
RD5/PSP5
(1)
/AD5
RD6/PSP6
(1)
/AD6
RD7/PSP7
(1)
/AD7
RE5/AD13/P1C
RH1/A17
RH0/A16
RE6/AD14/P1B
RE2/CS/AD10
RE4/AD12
RE3/AD11
RJ0/ALE
V
DD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18
RH3/A19
RE1/WR/AD9
RE0/RD/AD8
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG5/MCLR/V
PP
RG4/P1D
V
SS
V
DD
RF7/SS
RF6/AN11/C1IN-
RF5/AN10/C1IN+/CV
REF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
RH7/AN15/P1B
RH6/AN14/P1C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ2/WRL
RJ3/WRH
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2
(2)
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
V
SS
OSC2/CLKO/RA6
OSC1/CLKI
V
DD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RJ7/UB
RJ6/LB
PIC18F8X8X
RF1/AN6/C2OUT
RF0/AN5
RA2/AN2/V
REF
-
RC0/T1OSO/T13CKI
AV
SS
RA3/AN3/V
REF
+
RA5/AN4/LVDIN
RC6/TX/CK
Note 1:
PSP is available only in Microcontroller mode.
2:
CCP2 pin placement depends on the Processor mode settings.
RA4/T0CKI
RC1/T1OSI/CCP2
(2)
RC7/RX/DT
RA1/AN1
RH5/AN13
RH4/AN12
RA0/AN0
RJ4/BA0
DS39606E-page 4
RJ5/CE
AV
DD
V
DD
V
SS
RJ1/OE
V
SS
2010 Microchip Technology Inc.
PIC18FXX80/XX85
2.3
Memory Map
TABLE 2-2:
The code memory space extends from 0000h to
0FFFFh (64 Kbytes) in four 16-Kbyte blocks. However,
addresses 0000h through 07FFh define a “Boot Block”
region that is treated separately from Block 1. All of
these blocks define code protection boundaries within
the code memory space.
In contrast, code memory panels are defined in 8-Kbyte
boundaries. Panels are discussed in greater detail in
Section 3.2 “Code Memory Programming”.
IMPLEMENTATION OF CODE
MEMORY
Code Memory Size
(Bytes)
0000h - 00BFFFh (48K)
0000h -00FFFFh (64K)
Device
PIC18F6585
PIC18F8585
PIC18F6680
PIC18F8680
FIGURE 2-4:
000000h
MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FXX80/XX85 DEVICES
48 Kbytes
Code Memory
Boot Block
Panel 1
Block 1
Panel 2
Panel 3
Block 2
Unimplemented
Read as ‘0’
Block 3
Panel 6
Unimplemented
Read as ‘0’s
Block 4
Panel 8
00FFFFh
Panel 4
Panel 5
Block 3
Panel 6
00BFFFh
Panel 7
00DFFFh
Block 2
Panel 4
007FFFh
Panel 5
009FFFh
64 Kbytes
Boot Block
Block 1
Panel 1
Panel 2
003FFFh
Panel 3
005FFFh
000000h
0007FFh
001FFFh
00FFFFh
1FFFFFh
Configuration
and ID
Space
Unimplemented
Read as ‘0’s
Unimplemented
Read as ‘0’s
3FFFFFh
01FFFFh
Note:
Sizes of memory areas are not shown to scale.
2010 Microchip Technology Inc.
DS39606E-page 5
RF/无线
