PIC32MK GENERAL PURPOSE AND
MOTOR CONTROL (GP/MC) FAMILY
32-bit General Purpose and Motor Control Application MCUs with FPU and
up to 1 MB Live-Update Flash, 256 KB SRAM, 4 KB EEPROM, and Op amps
Operating Conditions: 2.2V to 3.6V
• -40ºC to +85ºC, DC to 120 MHz
• -40ºC to +125ºC, DC to 80 MHz
Security Features
• Advanced Memory Protection:
- Peripheral and memory region access control
Core: 120 MHz (up to 198 DMIPS)
• MIPS32
®
microAptiv™ MCU core with Floating Point Unit
• microMIPS™ mode for up to 40% smaller code size
• DSP-enhanced core:
- Four 64-bit accumulators
- Single-cycle MAC, saturating and fractional math
• Code-efficient (C and Assembly) architecture
• Two 32-bit core register files to reduce interrupt latency
Advanced Analog Features
• 12-bit ADC module:
- Sum of all individual ADC's combined, 25.45 Msps 12-bit mode
or 33.79 Msps 8-bit mode
- 7 individual ADC modules
- 3.75 Msps per S&H with dedicated DMA
- Up to 42 analog inputs
• Flexible and independent ADC trigger sources
• Four Op amps and five Comparators
• Up to three 12-bit CDACs
• Internal temperature sensor ±2ºC accuracy
• Capacitive Touch Divider (CVD)
Clock Management
• 8 MHz ±5% (FRC) internal oscillator 0ºC to +70ºC
• Programmable PLLs and oscillator clock sources:
- HS and EC clock modes
• Secondary USB PLL
• 32 kHz Internal Low-power RC oscillator (LPRC)
• Independent external low-power 32 kHz crystal oscillator
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timers (WDT) and Deadman Timer (DMT)
• Fast wake-up and start-up
• Four Fractional clock out (REFCLKO) modules
Communication Interfaces
• Up to four CAN modules (with dedicated DMA channels):
- 2.0B Active with DeviceNet™ addressing support
• Up to six UART modules (up to 25 Mbps):
- Supports LIN 1.2 and IrDA
®
protocols
• Six SPI/I
2
S modules (SPI 50 Mbps)
• Parallel Master Port (PMP)
• Up to two FS USB 2.0-compliant On-The-Go (OTG) controllers
• Peripheral Pin Select (PPS) to enable remappable pin functions
Power Management
• Low-power management modes (Deep Sleep, Sleep, and Idle)
• Integrated:
- Power-on Reset (POR) and Brown-out Reset (BOR)
• On-board capacitorless regulator
Timers/Output Compare/Input Capture/RTCC
• Up to 14 16-bit or one 16-bit and eight 32-bit timers/counters for GP
and MC devices and six additional QEI 32-bit timers for MC devices
• 16 Output Compare (OC) modules
• 16 Input Capture (IC) modules
• PPS to enable function remap
• Real-Time Clock and Calendar (RTCC) module
Motor Control PWM
•
•
•
•
•
•
•
Eight PWM pairs
Six additional Single-Ended PWM modules
Dead Time for rising and falling edges
Dead-Time Compensation
8.33 ns PWM Resolution
Clock Chopping for High-Frequency Operation
PWM Support for:
- DC/DC, AC/DC, inverters, PFC, lighting
- BLDC, PMSM, ACIM, SRM motors
• Choice of six Fault and Current Limit Inputs
• Flexible Trigger Configuration for ADC Triggering
Input/Output
•
•
•
•
5V-tolerant pins with up to 22 mA source/sink
Selectable internal open drain, pull-ups, and pull-downs
External interrupts on all I/O pins
Five programmable edge/level-triggered interrupt pins
Qualification and Class B Support
•
•
•
•
•
AEC-Q100 REVG (Grade 1 -40ºC to +125ºC) (planned)
Class B Safety Library, IEC 60730 (planned)
Back-up internal oscillator
Clock monitor with back-up internal oscillator
Global register locking
Motor Encoder Interface
• Six Quadrature Encoder Interface (QEI) modules:
- Four inputs: Phase A, Phase B, Home, and Index
Audio/Graphics/Touch Interfaces
•
•
•
•
External Graphics interfaces through PMP
Up to six I
2
S audio data communication interfaces
Up to six SPI audio control interfaces
Programmable audio master clock:
- Generation of fractional clock frequencies
- Can be synchronized with USB clock
- Can be tuned in run-time
Debugger Development Support
•
•
•
•
•
In-circuit and in-application programming
2-wire or 4-wire MIPS
®
Enhanced JTAG interface
Unlimited software and 12 complex breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Non-intrusive hardware-based instruction trace
Unique Features
• Permanent non-volatile 4-word unique device serial number
Software and Tools Support
•
•
•
•
•
C/C++ compiler with native DSP/fractional support
MPLAB
®
Harmony Integrated Software Framework
TCP/IP, USB, Graphics, and mTouch™ middleware
MFi, Android™ and Bluetooth
®
audio frameworks
RTOS Kernels: Express Logic ThreadX, FreeRTOS™,
OPENRTOS
®
, Micriµm
®
µC/OS™, and SEGGER embOS
®
Direct Memory Access (DMA)
• Up to eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)
• Up to 64 KB transfers
2016-2019 Microchip Technology Inc.
DS60001402G-page 1
Downloaded from
Arrow.com.
PIC32MK GP/MC Family
Packages
Type
Pin Count
I/O Pins (up to)
Contact/Lead Pitch
Dimensions
VQFN
64
48 (GP devices)
49 (MC devices)
0.50 mm
9x9x0.9 mm
64
48 (GP devices)
49 (MC devices)
0.50 mm
10x10x1 mm
TQFP
100
77 (GP devices)
78 (MC devices)
0.40 mm
12x12x1 mm
TABLE 1:
PIC32MK GENERAL PURPOSE (GP) FAMILY FEATURES
Timers/Capture/Compare
(1)
DMA Channels
(Programmable/Dedicated)
Remappable Peripherals
Floating Point Unit (FPU)
Boot Flash Memory (KB)
Program Memory (KB)
Data Memory (KB)
EE Memory (KB)
External Interrupts
(2)
Op amp/Comparator
Remappable Pins
USB 2.0 FS OTG
ADC (Channels)
JTAG/ICSP
Y
Y
Y
Y
JTAG/ICSP
Y
Y
Packages
REFCLK
I/O Pins
Device
CTMU
CDAC
RTCC
CAN 2.0B
PIC32MK0512GPD064 512 128
PIC32MK1024GPD064 1024 256
PIC32MK0512GPD100 512 128
PIC32MK1024GPD100 1024 256
PIC32MK0512GPE064 512 128
PIC32MK1024GPE064 1024 256
PIC32MK0512GPE100 512 128
PIC32MK1024GPE100 1024 256
Note
1:
2:
Legend:
4
4
4
4
Y
64
TQFP,
16
VQFN
Y
Y
Y
Y
9/16/16
9/16/16
9/16/16
9/16/16
6
6
6
6
SPI/I
2
S
UART
6
6
6
6
5
5
5
5
—
—
4
4
8/13
8/13
8/13
8/13
26 4/5
42 4/5
26 4/5
42 4/5
1
2
1
2
Y
Y
Y
Y
1
1
1
1
4
4
4
4
3
3
3
3
1
1
1
1
48
77
48
77
Y 100 TQFP 16
Y
64
TQFP,
16
VQFN
Y 100 TQFP 16
Eight out of nine timers are remappable.
Four out of five external interrupts are remappable.
An ‘—’ indicates this feature is not available for the listed device.
TABLE 2:
PIC32MK MOTOR CONTROL (MC) FAMILY FEATURES
Remappable Peripherals
Timers/Capture/Compare
(1)
DMA Channels
(Programmable/Dedicated)
Floating Point Unit (FPU)
Boot Flash Memory (KB)
Program Memory (KB)
Op amp/Comparator
Data Memory (KB)
EE Memory (KB)
External Interrupts
(2)
Remappable Pins
USB 2.0 FS OTG
ADC (Channels)
Packages
REFCLK
MCPWM
I/O Pins
Device
CTMU
CDAC
RTCC
CAN 2.0B
PIC32MK0512MCF064 512 128
PIC32MK1024MCF064 1024 256
PIC32MK0512MCF100 512 128
PIC32MK1024MCF100 1024 256
Note
1:
2:
4
4
Y
64
TQFP,
16
VQFN
Y 9/16/16 6
Y 9/16/16 6
SPI/I
2
S
UART
6
6
5
5
4
4
8/13 26 4/5 1
8/13 42 4/5 2
Y
Y
6
6
12
12
1
1
4
4
3
3
1
1
49
78
Y 100 TQFP 16
Eight out of nine timers are remappable.
Four out of five external interrupts are remappable.
DS60001402G-page 2
2016-2019 Microchip Technology Inc.
Downloaded from
Arrow.com.
Trace
Y
Y
PMP
Pins
QEI
Trace
Y
Y
Y
Y
PMP
Pins
PIC32MK GP/MC Family
Device Pin Tables
TABLE 3:
PIN NAMES FOR 64-PIN GENERAL PURPOSE (GPD/GPE) DEVICES
64-PIN VQFN
(4)
AND TQFP (TOP VIEW)
PIC32MK0512GPD064
PIC32MK0512GPE064
PIC32MK1024GPD064
PIC32MK1024GPE064
64
VQFN
(4)
Pin #
33
34
35
36
1
64
TQFP
Full Pin Name
1
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note
TCK/RPA7/PMD5/RA7
Full Pin Name
OA5IN+/DAC1/AN24/CVD24/C5IN1+/C5IN3-/RPA4/T1CK/
RA4
VBUS
VUSB3V3
D-
D+
VDD
OSCI/CLKI/AN49/CVD49/RPC12/RC12
OSCO/CLKO/RPC15/RC15
VSS
VBAT
PGD2/RPB5/USBID1/RB5
(7)
PGC2/RPB6/SCK2/PMA15/RB6
(6)
DAC2/AN48/CVD48/RPC10/PMA14/PMCS/RC10
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
SOSCI/RPC13(5)/RC13
(5)
SOSCO/RPB8(5)/RB8
(5)
TMS/OA5IN-/AN27/CVD27/C5IN1-/RPB9/RB9
TRCLK/RPC6/RC6
TRD0/RPC7/RC7
TRD1/RPC8/PMWR/RC8
TRD2/RPD5/PMRD/RD5
TRD3/RPD6/RD6
RPC9/RC9
VSS
VDD
RPF0/RF0
RPF1/RF1
RPB10/PMD0/RB10
RPB11/PMD1/RB11
RPB12/PMD2/RB12
RPB13/CTPLS/PMD3/RB13
TDO/PMD4/RA10
RPB14/VBUSON1/PMD6/RB14
RPB15/PMD7/RB15
AN19/CVD19/RPG6/PMA5/RG6
AN18/CVD18/RPG7/PMA4/RG7
MCLR
AN16/CVD16/RPG9/PMA2/RG9
VSS
VDD
AN10/CVD10/RPA12/RA12
AN9/CVD9/RPA11/RA11
OA2OUT/ANO/C2IN4-/C4IN3-/RPA0/RA0
OA2IN+/AN1/C2IN1+/RPA1/RA1
PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/RPB1/CTED1/PMA6/
RB1
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
AVDD
AVSS
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/PMA7/RC1
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/PMA13/RC2
AN11/CVD11/C1IN2-/PMA12/RC11
VSS
VDD
AN12/CVD12/C2IN2-/C5IN2-/PMA11/RE12
AN13/CVD13/C3IN2-/PMA10/RE13
(6)
AN14/CVD14/RPE14/PMA1/RE14
AN15/CVD15/RPE15/PMA0/RE15
TDI/DAC3/AN26/CVD26/RPA8/PMA9/RA8
(7)
RPB4/PMA8/RB4
1:
2:
3:
4:
5:
6:
7:
8:
(6)
(7)
(6)
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AN17/CVD17/RPG8/PMA3/RG8
(7)
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
13.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See
13.0 “I/O Ports”
for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V
SS
externally.
Functions are restricted to input functions only and inputs will be slower than the standard inputs.
The I
2
C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I
2
C master/slave clock, that is SCL.
The I
2
C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I
2
C data I/O, that is, SDA.
V
BAT
functionality is compromised. For additional information, refer to specific errata documents. This pin must be connected to V
DD
.
2016-2019 Microchip Technology Inc.
DS60001402G-page 3
Downloaded from
Arrow.com.
PIC32MK GP/MC Family
TABLE 4:
PIN NAMES FOR 64-PIN MOTOR CONTROL (MCF) DEVICES
64-PIN VQFN
(4)
AND TQFP (TOP VIEW)
PIC32MK0512MCF064
PIC32MK1024MCF064
64
64
VQFN
(4)
Pin
#
34 VBUS
1
TQFP
Full Pin Name
1
Pin
#
1
2
3
4
5
6
7
8
9
Full Pin Name
TCK/RPA7/PWM10H/PWM4L/PMD5/RA7
RPB14/PWM1H/VBUSON1/PMD6/RB14
RPB15/PWM7H/PWM1L/PMD7/RB15
AN19/CVD19/RPG6/PMA5/RG6
AN18/CVD18/RPG7/PMA4/RG7
(6)
AN17/CVD17/RPG8/PMA3/RG8
(7)
MCLR
AN16/CVD16/RPG9/PMA2/RG9
VSS
33 OA5IN+/DAC1/AN24/CVD24/C5IN1+/C5IN3-/RPA4/T1CK/RA4
35 VUSB3V3
36 D-
37 D+
38 VDD
39 OSCI/CLKI/AN49/CVD49/RPC12/RC12
40 OSCO/CLKO/RPC15/RC15
41 VSS
42 RD8
43 PGD2/RPB5/USBID1/RB5
(7)
44 PGC2/RPB6/SCK2/PMA15/RB6
(6)
45 DAC2/AN48/CVD48/RPC10/PMA14/PMCS/RC10
46 OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
47 SOSCI/RPC13
(5)
/RC13
(5)
48 SOSCO/RPB8
(5)
/RB8
(5)
49 TMS/OA5IN-/AN27/CVD27/C5IN1-/RPB9/RB9
50 TRCLK/RPC6/PWM6H/RC6
51 TRD0/RPC7/PWM12H/PWM6L/RC7
52 TRD1/RPC8/PWM5H/PMWR/RC8
53 TRD2/RPD5/PWM12H/PMRD/RD5
54 TRD3/RPD6/PWM12L/RD6
55 RPC9/PWM11H/PWM5L/RC9
56 VSS
57 VDD
58 RPF0/PWM11H/RF0
59 RPF1/PWM11L/RF1
60 RPB10/PWM3H/PMD0/RB10
61 RPB11/PWM9H/PWM3L/PMD1/RB11
62 RPB12/PWM2H/PMD2/RB12
63 RPB13/PWM8H/PWM2L/CTPLS/PMD3/RB13
64 TDO/PWM4H/PMD4/RA10
10 VDD
11 AN10/CVD10/RPA12/RA12
12 AN9/CVD9/RPA11/USBOEN1/RA11
13 OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
14 OA2IN+/AN1/C2IN1+/RPA1/RA1
15 PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
16 PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/RPB1/CTED1/PMA6/RB1
17 PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
18 PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
19 AVDD
20 AVSS
21 OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
22 OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/PMA7/RC1
23 OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/FLT3/PMA13/RC2
24 AN11/CVD11/C1IN2-/FLT4/PMA12/RC11
25 VSS
26 VDD
27 AN12/CVD12/C2IN2-/C5IN2-/FLT5/PMA11/RE12
(7)
28
AN13/CVD13/C3IN2-/FLT6/PMA10/RE13
(6)
29 AN14/CVD14/RPE14/FLT7/PMA1/RE14
30 AN15/CVD15/RPE15/FLT8/PMA0/RE15
31
TDI/DAC3/AN26/CVD26/RPA8/PMA9/RA8
(7)
1:
2:
3:
4:
5:
6:
7:
32 FLT15/RPB4/PMA8/RB4
(6)
Note
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
13.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See
13.0 “I/O Ports”
for more information.
Shaded pins are 5V tolerant.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V
SS
externally.
Functions are restricted to input functions only and inputs will be slower than standard inputs.
The I
2
C Library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I
2
C master/slave clock, that is, SCL.
The I
2
C Library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I
2
C data I/O, that is, SDA.
DS60001402G-page 4
2016-2019 Microchip Technology Inc.
Downloaded from
Arrow.com.
PIC32MK GP/MC Family
TABLE 5:
PIN NAMES FOR 100-PIN GENERAL PURPOSE (GPD/GPE) DEVICES
100-PIN TQFP (TOP VIEW)
PIC32MK0512GPD100
PIC32MK0512GPE100
PIC32MK1024GPD100
PIC32MK1024GPE100
100
M
1
Pin #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
VSS
VDD
AN35/CVD35/RG11
AN36/CVD36/RF13
AN37/CVD37/RF12
AN12/CVD12/C2IN2-/C5IN2-/SDA4/PMA11/RE12
(6)
AN13/CVD13/C3IN2-/SCL4/PMA10/RE13
(5)
AN14/CVD14/RPE14/PMA1/RE14
AN15/CVD15/RPE15/PMA0/RE15
VSS
VDD
AN38/CVD38/RD14
AN39/CVD39/RD15
TDI/DAC3/AN26/CVD26/RPA8/SDA2/PMA9/RA8
(6)
RPB4/SCL2/PMA8/RB4
(5)
OA5IN+/DAC1/AN24/CVD24/C5IN1+/C5IN3-/RPA4/T1CK/RA4
AN40/CVD40/RPE0/RE0
AN41/CVD41/RPE1/RE1
VBUS1
VUSB3V3
D1-
D1+
VBUS2
D2-
D2+
AN45/CVD45/RF5
VDD
OSCI/CLKI/AN49/CVD49/RPC12/RC12
OSCO/CLKO/RPC15/RC15
VSS
AN46/CVD46/RPA14/RA14
AN47/CVD47/RPA15/RA15
VBAT
PGD2/RPB5/SDA3/USBID1/RB5
(6)
PGC2/RPB6/SCL3/SCK2/PMA15/RB6
(5)
Full Pin Name
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Note
VDD
TCK/RPA7/PMD5/RA7
Full Pin Name
AN23/CVD23/PMA23/RG15
RPB14/VBUSON1/PMD6/RB14
RPB15/PMD7/RB15
RD1
RD2
RPD3/RD3
RPD4/RD4
AN19/CVD19/RPG6/VBUSON2/PMA5/RG6
AN18/CVD18/RPG7/SCL1/PMA4/RG7
MCLR
AN16/CVD16/RPG9/PMA2/RG9
VSS
VDD
AN22/CVD22/RG10
AN21/CVD21/RE8
AN20/CVD20/RE9
AN10/CVD10/RPA12/RA12
AN9/CVD9/RPA11/RA11
OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
OA2IN+/AN1/C2IN1+/RPA1/RA1
PGD3/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
PGC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPB1/CTED1/RB1
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
VREF-/AN33/CVD33/PMA7/RF9
VREF+/AN34/CVD34/PMA6/RF10
AVDD
AVSS
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/RC1
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/PMA13/RC2
AN11/CVD11/C1IN2-/PMA12/RC11
1:
2:
3:
4:
5:
6:
7:
(5)
(6)
AN17/CVD17/RPG8/SDA1/PMA3/RG8
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
13.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See
13.0 “I/O Ports”
for more information.
Shaded pins are 5V tolerant.
Functions are restricted to input functions only and inputs will be slower than standard inputs.
The I
2
C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I
2
C master/slave clock, that is, SCL.
The I
2
C library is available in MPLAB Harmony. For future hardware or silicon compatibility, it is recommended to use these pins for the
I
2
C data I/O, that is, SDA.
V
BAT
functionality is compromised. For additional information, refer to specific errata documents. This pin must be connected to V
DD
.
2016-2019 Microchip Technology Inc.
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