Very low Jitter and Phase Noise (< 40ps Pk -Pk typ.)
Supports complementary LVCMOS outputs to drive
LVPECL and LVDS inputs.
Output Frequencies:
o
< 400MHz at 3.3V
o
< 350MHz at 2.5V
Input Frequencies:
o
Fundamental Crystal: 10MHz - 30MHz
o
3
RD
overtone Crystal: Up to 75MHz
o
Reference Input: Up to 200MHz
Accepts <1.0V reference signal input voltage
One programmable I/O pin can be configured as
Output Enable (OE) input, Frequency Selection
(FSEL) input or Reference Clock (CLK2) output.
Single 2.5V or 3.3V ± 10% power supply
Operating temperature range from -40C to 85C
Available in 8-pin MSOP/SOP Green/RoHS compliant
packages.
PIN CONFIGURATION
XIN, FIN
GND
CLK0
K
CLK1
1
8
XOUT
OE, FSEL, CLK2
DNC
VDD
PL611-30
2
3
4
7
6
5
(M)SOP-8L
DESCRIPTION
The PL611-30 is a low-cost general purpose frequency synthesizer and a member of Programmable Clock family.
2
PL611-30 product family can generate any output frequency up to 400MHz from fundamental crystal input
0
between 10MHz - 30MHz, a 3rd overtone crystal of up to 75MHz (3.3V Only) or a Reference Clock from 1MHz to
200MHz. The PL611-30 produces complementary LVCMOS outputs to support LVPECL, LVDS, and LVCMOS
inputs.
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
Osc
F
REF
R-Counter
(8-bit)
Phase
Detector
M-Counter
(11-bit)
Charge
Pump
Loop
Filter
Programming
Logic
FSEL
OE
CLoad
F
VCO
= F
REF
* (4M/R)
VCO
P-Counter
(5-bit)
F
out
= F
VCO
/ (4*P)
Input Logic
Control
CLK[0:1]
OE, FSEL, CLK2
Programmable Function
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev. 01/12/12 Page 1
PL611-30
Programmable Clock
KEY PROGRAMMING PARAM ETERS
CLK[0:2]
Output Frequency
F
OUT
= F
IN
* M / (R * P)
where M= 11 bit
R= 8 bit
P= 5 bit
1. CLK[0:1]= F
V CO
/ (4 * P)
or F
V CO
/2
2. CLK[2]= F
REF
Output Drive
Strength
Std: 10mA
(default)
High: 24mA
Crystal
Load
Programmable
Input/Output (pin #7)
# of
Register
Banks
2
Charge-Pump
Current
8 levels of
charge-pump
current setting
± 200ppm One output pin can be
tuning.
configured as
1. CLK2 - output
2. FSEL - input
3. OE - input
PIN DESCRIPTION
Name
XIN, FIN
GND
CLK[0:1]
VDD
DNC
Pin #
(M)SOP-8L
1
2
3,4
5
6
Type
I
P
O
P
-
Description
Crystal or Reference input pin
GND connection
Programmable Clock Output [note:CLK0=~CLK1]
VDD connection
Do No Connect
This programmable I/O pin can be configured as Output Enable
(OE) input, Frequency Select (FSEL) input or CLK2 (F
REF
) output.
This pin has an internal 60KΩ pull up resistor when used as OE or
FSEL.
OE, FSEL, CLK2
7
B
State
0
1 (default)
XOUT
8
O
OE
Tristate CLK[0:1]
Normal mode
FSEL
Select Bank ’0’
Select Bank ‘1’
Crystal output pin. Do Not Connect when using F
IN
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev. 01/12/12 Page 2
PL611-30
Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Data Retention @ 85º C
Soldering Temperature
Storage Temperature
Ambient Operating Temperature*
T
S
-65
-40
SYMBOL
V
DD
V
I
V
O
MIN.
-0.5
-0.5
-0.5
10
240
150
+85
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
UNITS
V
V
V
Years
C
C
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency
Input (F
IN
) Frequency
Input (F
IN
) Signal Amplitude
Output Frequency
OE Enable Time
Settling Time
VDD Sensitivity
Output Rise Time
Output Fall Time
Duty Cycle
Max. output skew between
same frequency clocks
Period Jitter, peak-to-peak*
(10,000 samples measured)
Internally AC coupled
At 3.3V V
DD
, 15pF Load
At 2.5V V
DD
, 15pF Load
OE Function; Ta=25º C, 15pF Load. Add
one clock period to this measurement for a
usable clock output.
At power-up (V
DD
> 2.25V)
Frequency vs. V
DD
+/-10%
15pF Load, 10/90%V
DD
, Standard Drive
15pF Load, 10/90%V
DD
, High Drive
15pF Load, 90/10%V
DD
, Standard Drive
15pF Load, 90/10%V
DD
, High Drive
At V
DD
/2
Equal loading (15pF). Equal frequency &
drive strength
With capacitive decoupling between V
DD
and GND. Operating only CLK[0:1] outputs.
40
45
0.9
3
3
CONDITIONS
Fundamental Crystal
3
rd
Overtone Crystal (3.3V Operation Only)
MIN.
10
TYP.
MAX.
30
75
200
V
DD
400
350
10
10
-2
2.5
1.0
2.5
1.0
50
2
3.5
1.5
3.5
1.5
55
500
UNITS
MHz
MHz
Vpp
MHz
ns
ms
ppm
ns
ns
%
ps
ps
* Note: Jitter perform ance depends on the programming parameters.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev. 01/12/12 Page 3
PL611-30
Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current,
Dynamic, with Loaded
Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current
SYMBOL
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OHD
I
OL
= +4mA (Standard Drive)
I
OH
= -4mA (Standard Drive)
V
OL
= 0.4V, V
OH
= 2.4V (Standard Drive)
V
OL
= 0.4V, V
OH
= 2.4V (High Drive)
V
DD
-0.4
10
24
CONDITIONS
At 10MHz, load=15pF
2.25
MIN.
TYP.
MAX.
15
3.63
0.4
UNITS
mA
V
V
V
mA
mA
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
3
rd
Overtone Crystal Resonator Frequency (3.3V Only)
Crystal Loading Rating
(The IC can be programmed for any value in this range.)
SYMBOL
F
XIN
F
XIN
C
L (x ta l)
MIN.
10
TYP.
MAX.
30
75
UNITS
MHz
MHz
pF
W
W
pF
Ω
Ω
Ω
Ω
5
20
500
100
Maximum Sustainable Drive Level
Operating Drive Level
Crystal Shunt Capacitance
Effective Series Resistance, Fundamental,
10MHz - 30MHz
Effective Series Resistance, 3
rd
Overtone,
30MHz - 50MHz [CO< 4pF, C
L
=5pF/8pF]
Effective Series Resistance, 3
rd
Overtone,
50MHz - 65MHz, [CO< 4pF, C
L
=5pF/8pF]
Effective Series Resistance, 3
rd
Overtone,
65MHz - 75MHz [CO< 4pF, C
L
=5pF/8pF]
C0
ESR
ESR
ESR
ESR
6
30
100/70
60/40
45/30
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev. 01/12/12 Page 4
PL611-30
Programmable Clock
TERMINATING COM PLEMENTARY LVCM OS OUTPUTS
Figure 1 below describes how to terminate the complementary LVCMOS outputs of PL611-30 Programmable
Clock for use with LVPECL or LVDS inputs.
The unique feature of complementary LVCMOS outputs allows great flexibility for board designers. By
standardizing on one termination scheme you can use the PL611 -30 for all your LVDS and LVPECL clock
requirements up to 400MHz.
+3.3V
LVCMOS Output
R1
50 Ohm line
R2
Input
R3
Complementary
LVCMOS Output
R1
50 Ohm line
R3
Complementary
Input
LVPECL LVDS
2.35V 1.40V
1.59V 1.10V
3.3V
0V
Component selection
For LVPECL input For LVDS input
R1 = 130 Ohm
R2 = 82 Ohm
R3 = 130 Ohm
R1 = 360 Ohm
R2 = 130 Ohm
R3 = 82 Ohm
R2
+3.3V
Notes:
Place R1 as close to the LVCMOS outputs as
possible.
Place R2 and R3 as close to the LVPECL/LVDS
inputs as possible.
Figure 1
The above layout allows the PL611-30 to drive either LVPECL or LVDS inputs by simply changing the value of R1.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
