PLC810PG
HiperPLC
™
Family
Continuous Mode PFC & LLC Controller
with Integrated Half-bridge Drivers
Product Highlights
Features
•
Highly integrated, eliminates external components
•
Frequency and phase synchronized PFC and LLC
•
Reduced noise and EMI
•
Ripple current reduction in PFC output capacitor
•
Edge collision-avoidance simplifies layout
•
Comprehensive PFC and LLC fault handling and current limiting
•
Proprietary continuous conduction mode PFC for high
efficiency with low component cost
•
High efficiency Zero Voltage Switching (ZVS) LLC
•
Off-time PFC control eliminates AC input sensing components
•
Configurable, precise dead time control and frequency limit
•
Prevents hard MOSFET switching
•
Tight LLC duty cycle symmetry for balanced O/P diode currents
•
Lead and halogen free Green package
Applications
•
32” to 60” LCD TV power supplies
•
Off-line 150 W to 600 W efficiency-optimized power supplies
•
LED street lighting
Description
The PLC810PG is a combined PFC and LLC off-line controller
with integrated high voltage half-bridge drivers. Figure 1 shows
a simplified schematic of a PLC810PG based power supply
where the LLC resonant inductor is integrated into the
transformer. The PFC section of the PLC810PG is a universal
input continuous current mode (CCM) design that does not
require a sinusoidal input reference, thereby reducing system
cost and external components.
The DC-DC controller drives an LLC resonant topology. This
variable frequency controller provides high efficiency by
switching the power MOSFETs at zero voltage, eliminating most
switching losses. The LLC controller is built around a current
controlled oscillator with a control range selected to support
the traditional frequency of operation found in televisions.
To ensure zero voltage switching, the dead time of the LLC
switching in the PLC810PG is tightly toleranced and can be
adjusted with an external resistor. The highside/lowside duty
cycle is also closely matched to provide balanced output
currents reducing output diode cost.
A typical PLC810PG LLC design operates at 100 kHz (under
nominal conditions). Depending on the LLC circuit design, the
switching frequency can vary from half to three times the nominal
operating frequency as a result of line and load changes.
The PFC converter is frequency locked to the LLC to minimize
noise and electromagnetic interference. Increasing the PFC
frequency in synchronization with the LLC at light loads
reduces the current at which the PFC boost converter
Standby
Supply
AC
IN
VCCHB
GATEH
HB
VCCL
VCC
ISP
FBP
PFC Gate
Driver
GATEP
GATEL
ISL
VREF
+
DC
OUT
PLC810PG
VCOMP
FMAX
FBL
LLC Feedback Circuit
GNDP
GND
Link
Figure 1.
Typical Application Circuit – LCD TV Power Supply.
August 2009
GNDL
PI-5044a-121708
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PLC810PG
becomes discontinuous improving light load operation and
reducing power line harmonics. PFC and LLC primary side fault
management is provided.
The phase of the PFC PWM output is dynamically adjusted
relative to the LLC phase such that the switching edges do not
coincide with noise sensitive events in the PWM and LLC timing
circuits. This edge-collision avoidance technology simplifies
power supply layout and improves performance. Phase
synchronization reduces EMI spectral components and reduces
ripple current in the PFC capacitor.
2
Rev. F 08/09
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PLC810PG
Pin Description
VCC Pins
VCC
VCC powers the small signal analog circuitry inside the IC. A
bypass capacitor must be connected from the VCC pin to the
GND pin. This capacitor needs to be a 10
mF
ceramic capacitor,
or a parallel combination of a 10
mF
electrolytic capacitor and a
0.1
mF
ceramic capacitor.
VCCL
VCCL is the supply pin for the LLC low side driver. It powers only
the LLC low side MOSFET driver and the communications circuitry
between the analog circuitry and the LLC drivers. A 1
mF
ceramic
bypass capacitor must be connected from the VCCL pin to the
GNDL pin. This capacitor provides the instantaneous current for
turning on the gate of the LLC low-side MOSFET.
VCCHB
VCCHB is the floating supply pin for the LLC high-side driver,
which is referenced to the HB pin. The HB pin is in turn
connected to the LLC MOSFET half-bridge center point. A 1
mF
ceramic bypass capacitor must be connected from the VCCHB
pin to the HB pin. This capacitor provides the instantaneous
current for turning on the gate of the high side LLC MOSFET.
In a typical application, VCC is connected to the standby
supply. VCCL should be connected to the VCC pin through a
5
W
resistor for noise immunity. VCCHB is connected to the
standby supply through a series combination of a high voltage
diode and a 5
W
resistor. This diode plus resistor combination
charges the 1
mF
decoupling capacitor whenever the LLC low-
side MOSFET is on. The resistor limits the peak instantaneous
charging current. See R42 and D8 in Figure 4.
GND Pins
GND
GND is the return node for all analog small signals. All small
signal pin bypass capacitors must be connected to this pin via
short traces. This pin must have a single point connection, via
a dedicated trace to the PFC current sense resistor, which in
turn must be placed close to the PFC MOSFET. It must not be
connected to any other point in the PFC/LLC power train. The
VCC bypass capacitor must also be connected to this pin.
GNDP
GNDP is the return for the PFC gate drive signal
only.
This pin
must be connected on the PCB directly to the GND pin.
GNDL
GNDL is the return for the LLC low side gate driver only. This pin
must be connected to the LLC low side MOSFET Source pin,
with a dedicated trace, and a small ferrite bead. This pin must be
connected to the GND pin via a 1
W
resistor for noise immunity.
The VCCL bypass capacitor must also be returned to this pin.
Other Pins
HB
Half-bridge pin. This pin is the return of the LLC high side
MOSFET driver. It must be connected to the center of the half-
bridge formed by the LLC MOSFETs. The VCCHB bypass
capacitor must also be returned to this pin.
ISP
Current sense, PFC. It is for sensing the negative voltage on
the current sense resistor (which describes PFC inductor
current). This sense resistor is connected between PFC
MOSFET Source and Bridge ‘-’ terminal. The signal must pass
through an RC low-pass filter with a time constant between 100
and 200 ns. The resistor must be no greater than 150
W
due to
internal offset current requirements for the ISP pin. The average
inductor current (measured over several switching cycles) is
used for the PFC control algorithm. This pin also Implements
pulse-by-pulse current limiting.
ISL
Current sense, LLC. This pin is for sensing transformer primary
current, to detect LLC overload. It should be connected to the
current sense resistor, which is connected between the LLC low
side MOSFET Source pin and the bottom side of the trans-
former primary. The signal must pass through an RC low-pass
filter with a time constant between 200 ns and 1
ms.
The
capacitor in the low-pass filter must be connected to the GND
pin. The current limit has 2 levels, a lower, slow current limit for
output overload, and a higher, fast current limit for component
failure protection. The series resistor in the low-pass filter
should be 1 kW or greater to limit current into the ISL pin.
GATEP
Gate drive output signal for the PFC MOSFET gate drive circuit.
GATEL
Gate drive for the low side LLC MOSFET.
GATEH
Gate drive for the high side LLC MOSFET.
VREF
3.3 V reference pin for the LLC feedback circuitry. A 1
mF
ceramic decoupling capacitor must be connected from the V
REF
pin to the GND pin.
FBP
The Feedback PFC pin is connected to the external resistor
divider that senses PFC output voltage. This is a non-inverting
input to a transconductance amplifier. The transconductance
amplifier output is connected to the VCOMP pin, to which the
feedback compensation is also connected. A 10 nF decoupling
capacitor must be connected from the FBP pin to the GND pin.
VCOMP
This pin is the connection point for PFC feedback loop
components. The voltage on this pin is used as an input to the
PFC controller multiplier. The linear voltage range for this pin is
nominally 0.5 V to 2.5 V, where higher voltage signifies less power.
FBL
LLC Feedback pin. Current entering this pin determines LLC
switching frequency. It has a Thevenin equivalent circuit of
nominally 0.65 V and 3.3 kW. FBL must be decoupled to the
GND pin with a 1 nF capacitor. Note that this capacitor forms a
pole with the input resistance.
3
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Rev. F 08/09
PLC810PG
FMAX
This pin is for programming maximum LLC frequency with a
resistor to VREF. If the frequency commanded by the FBL pin
current exceeds 95% of the programmed maximum frequency,
the LLC high and low side drivers turn both LLC MOSFETs off.
This pin must be decoupled to the GND pin with a 1 nF
capacitor.
RSVD1, RSVD2, and RSVD3
RSVD1 must be connected to VREF. RSVD2 and RSVD3 must
be connected to the GND pin.
VCOMP
GND
ISP
VREF
RSVD1
GATEP
VCC
GNDP
GNDL
GATEL
NC
GATEH
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC
FBP
ISL
FMAX
FBL
GND
RSVD3
RSVD2
VCCL
NC
HB
VCCHB
PI-5040-012709
Figure 2.
Pin Numbering and Designation (Top View).
4
Rev. F 08/09
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PLC810PG
ISP (3)
VCOMP (1)
FBP (23)
INVERSION
PFC FAULT
DVGA
and LPF
+
OTA
V
FBPREF
-
+
-
V
OVH
V
IN(H)
/V
IN(L)
GND (2,19)
V
SD(H)
V
SD(L)
+
-
+
-
V
REF
SOFT ONE SHOT
4096
START
CYCLES
(13) VCCHB
OVL FAULT
RAMP AND CLOCK
GENERATOR
DEAD TIME
GENERATOR
NON-
OVERLAP
GENERATOR
FBL (20)
FMAX (21)
LLC CURRENT
FEEDBACK
ISL (22)
V
ISL(F)
V
ISL(S)
Figure 3.
Block Diagram of PLC810PG. Reserved Pins are not Shown.
Block Diagram
Figure 3 shows a block diagram of the functional elements that
make up the PLC810PG. The reserved pins are not shown in
the diagram. Those pins are reserved for PI use during
manufacture and testing. The PLC810PG PFC control blocks
and circuits are shown on the upper half of the block diagram,
while the LLC control blocks are shown on the lower half. Some
of the functional blocks are shared.
PLC810PG Power Block
The PLC810PG is powered through VCC and VCCL pins. The
VCCL pin powers the LLC driver while VCC powers the rest of the
device. VCC pin must be supplied by a voltage between V
UVLO(+)
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+
-
V
OC
OC FAULT
LLC CLOCK
PWM
PHASE
ALIGNMENT
(6) GATEP
(7) VCC
OV FAULT
UVLO
RESET
+
PFC INHIBIT
INTERNAL REFERENCE
GENERATOR
LLC OFF
-
V
UVLO(+)
V
UVLO(-)
(8) GNDP
3.3 V LINEAR
REGULATOR
(4) VREF
(12) GATEH
(14) HB
(16) VCCL
+
(10) GATEL
CLAMP
(9) GNDL
LLC FAULT
1.2 V
-
+
-
CLAMP
LLC OFF
OVL FAULT
PI-5041-112608
and 15 V. The provided supply is continuously compared against
the V
UVLO(+)
and V
UVLO(-)
thresholds to start/stop the PLC810PG.
When VCC is above the V
UVLO(+)
threshold the PLC810PG de-
asserts the undervoltage lockout (UVLO) signal allowing the device
to start. If VCC falls below V
UVLO(-)
, the UVLO signal is asserted,
shutting down the PLC810PG.
The VCCL pin powers the LLC driver, and VCCHB provides the
charge for the LLC high-side MOSFET for gate drive.
An internal linear regulator is used to generate a 3.3 V rail to power
the low voltage circuits inside the PLC810PG. The 3.3 V is brought
outside on the VREF pin allowing external low voltage circuits to be
powered by the PLC810PG.
5
Rev. F 08/09
