range, providing less than -130dBc at 10kHz offset
when using a 35.328MHz crystal. The very low jitter
(2.5 ps RMS period jitter) makes this chip ideal for
applications requiring voltage controlled frequency
sources. Input crystal can range from 16MHz to
36MHz (fundamental resonant mode).
SOT23-6*
^: Denotes internal Pull-up
*: SOT package offers single divider option only
DIVIDER SELECTION LOGIC LEVELS
Part #
PLL500-15
PLL500-16
DivSel State
1 (Default)
0
1 (Default)
0
Operation
÷16
÷8
÷4
÷2
BLOCK DIAGRAM
DIVSEL
XIN
VCXO
XOUT
VCON
Varicap
Selectable
Divider
CLK
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/12/06 Page 1
(Preliminary)
PLL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
DIE PAD LAYOUT
DIE SPECIFICATIONS
Name
Value
32 mil
(812,986)
8
1
XIN
XOUT
OE^ 7
39 mil
2
VCON
VDD 6
Size
Reverse side
Pad dimensions
Thickness
39 x 32 mil
GND
80 micron x 80 micron
10 mil
3 DIVSEL^
4 GND
CLK 5
DIE ID: PLL500-15: C500A A1111-12
PLL500-16: C500A A1111-11
Y
X
(0,0)
Note: ^ denotes internal pull up
PACKAGE PIN and DIE PAD ASSIGNMENT
Pin#
Name
XIN
VCON
DIVSEL
GND
CLK
VDD
OE
XOUT
Die Pad Position
X (µm)
94.183
94.157
94.183
94.193
715.472
715.307
715.472
476.906
SOP-8
1
2
3
4
5
6
7
8
SOT23-6
6
5
-
4
3
2
-
1
Y (µm)
768.599
605.029
331.756
140.379
203.866
455.726
626.716
888.881
Type
I
P
I
P
O
P
I
I
Crystal input pin.
Description
Frequency Control Voltage input pin.
Divider Selection input pin. Default Logic 1 for
SOT23 package. See Divider Selection Logic
Levels table on Page 1.
Ground pin.
Output clock pin.
VDD power supply pin.
Output Enable input pin. Disables the output when
low. Internal pull-up enables output by default if
pin is not connected to low. Default “Enabled”
(Logic 1) for SOT23 package.
Crystal output pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/12/06 Page 2
(Preliminary)
PLL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Output Clock Rise/Fall Time
Output Clock Duty Cycle
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V
45
SYMBOL
CONDITIONS
MIN.
16
TYP.
1.15
3.7
50
MAX.
36
UNITS
MHz
ns
55
%
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
Power Supply Rejection
VCON pin input impedance
VCON modulation BW
PWSRR
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
MIN.
TYP.
300
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
ppm
kΩ
kHz
±150
100
5
Frequency change with
VDD varied +/- 10%
0V
≤
VCON
≤
3.3V, -3dB
-1
2000
45
+1
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/12/06 Page 3
(Preliminary)
PLL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
4. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling between
VDD and GND.
18MHz @100Hz offset
18MHz @1kHz offset
18MHz @10kHz offset
18MHz @100kHz offset
18MHz @1MHz offset
MIN.
TYP.
2.5
-75
-105
-125
-133
-140
MAX.
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
5. DC Specifications
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
Operating Voltage
Output Low Voltage at
CMOS level
Output High Voltage at
CMOS level
Output drive current
VCXO Control Voltage
SYMBOL
I
DD
V
DD
V
OLC
V
OHC
VCON
CONDITIONS
F
XIN
= 36MHz
Output load of 15pF
MIN.
TYP.
5
MAX.
6
3.63
0.4
UNITS
mA
V
V
V
2.25
I
OL
= +4mA
I
OH
= -4mA
For V
OL
<0.4V or V
OH
>2.4V
V
DD
– 0.4
8
0
9.5
V
DD
mA
V
6. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating (VCON = 1.65V)
Maximum Sustainable Drive Level
Operating Drive Level
C0
C0/C1
ESR
SYMBOL
F
XIN
C
L (xtal)
MIN.
16
TYP.
8.5
MAX.
36
200
UNITS
MHz
pF
µW
µW
pF
-
Ω
50
5
250
30
R
S
Note:
The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/12/06 Page 4
(Preliminary)
PLL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOIC 8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
SOT-23 6L
Symbol
A
A1
A2
B
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.05
1.35
0.05
0.15
1.00
1.20
0.30
0.50
0.08
0.20
2.80
3.00
1.50
1.70
2.60
3.00
0.35
0.55
0.95 BSC
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
E
H
D
A2 A
A1
e
b
C
L
E
H
D
A2 A
A1
e
b
C
L
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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