Part Number 460GT
Revision 1.07 – May 29, 2008
460GT
PowerPC 460GT Embedded Processor
Features
• PowerPC
®
440 processor operating between
667MHz and 1GHz with 32KB I-cache and D-
cache and 256KB L2/SRAM with parity checking
• On-chip memory (64KB)
• Processor Local Bus (PLB) with 128-bit width
• Floating Point unit
• Double Data Rate 2/1 (DDR2/1) Synchronous
DRAM (SDRAM) interface
• One four-channel DMA (Direct Memory Access)
for internal and external peripherals
• One single-channel, high-performance DMA for
internal use
• External 32-bit peripheral bus (EBC) for up to six
devices. Up to 100MHz
• Programmable Interrupt Controller (UIC) with up
to 16 external interrupts
• Programmable General Purpose Timers (GPTs)
• Two PCI Express 1.1 interfaces—one 4-lane and
one 1-lane
Preliminary Data Sheet
• PCI V2.3 interface. Thirty-two bits at up to 66MHz
• Four Ethernet 10/100/1000Mbps half- or full-
duplex interfaces. Operational modes supported
are MII, RMII, GMII, RGMII, and SGMIII with QoS,
Jumbo frames, interrupt coalescing, and TCP/IP
acceleration
• Up to four serial (UART) ports (16750 compatible)
• Two IIC interfaces (one with boot parameter read
capability)
• NAND Flash interface
• SPI interface
• Serial Rapid I/O (SRIO) port
• General Purpose I/O (GPIO) interface
• JTAG interface for board level testing
• Boot from PCI memory, NOR Flash on the
external peripheral bus, or NAND Flash on the
NAND Flash interface
• Optional security feature (PPC460GT-S) with
KASUMI.
• Available in RoHS compliant, lead-free package
Description
Designed specifically to address high-end embedded
applications, the PowerPC 460GT (PPC460GT)
provides a high-performance, low-power solution that
interfaces to a wide range of peripherals and
incorporates on-chip power management features.
This chip contains a high-performance RISC
processor, a floating point unit, on-chip memory, a
DDR2/1 SDRAM controller, PCI and PCI Express bus
interfaces, control for external ROM and peripherals,
DMA with scatter/gather support, Ethernet ports, serial
ports, IIC interfaces, SPI interface, NAND Flash
interface, SRIO support, an optional security feature
with KASUMI (PPC460GT-S), and general purpose
I/O.
Technology: CMOS Cu-08, 90nm.
Package: 35mm, 728-ball thermally and electrically
enhanced plastic ball grid array (TE-EPBGA). RoHS
compliant package available.
Typical power: Less than 6W at 1GHz.
Supply voltages required: 3.3V, 2.5V (DDR1,
Ethernet), 1.8V (DDR2), 1.2V.
AMCC Proprietary
1
460GT – PPC460GT Embedded Processor
Revision 1.07 – May 29, 2008
Preliminary Data Sheet
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PowerPC 440 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
L2 Cache/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Security Function (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PCI Express Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DDR2/1 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DMA 4-Channel Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial Ports (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IIC Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Peripheral Controller (SPI/SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DDR2/1 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2
AMCC Proprietary
Revision 1.07 – May 29, 2008
460GT – PPC460GT Embedded Processor
Preliminary Data Sheet
Figures
Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. PPC460GT Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. 35mm, 728-Ball TE-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 6. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 7. Input Setup and Hold Timing Waveform for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 8. Output Delay and Hold Timing Waveform for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 9. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 10. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 12. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 13. DDR SDRAM Read Cycle Timing—Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Tables
Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 5. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 7. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 10. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 11. Typical DC Power Supply Requirements Using DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 12. Typical DC Power Supply Requirements Using DDR1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 13. V
DD
Supply Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 14. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 15. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 16. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 17. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 18. I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 19. I/O Specifications—400MHz to 1000MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 20. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 21. DDR SDRAM Write Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 22. I/O Timing—DDR SDRAM T
DS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 23. I/O Timing—DDR SDRAM T
SA
, and T
HA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 24. I/O Timing—DDR SDRAM Write Timing T
SD
and T
HD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 25. I/O Timing—DDR SDRAM Read Timing T
SD
and T
HD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 26. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
AMCC Proprietary
3
460GT – PPC460GT Embedded Processor
Revision 1.07 – May 29, 2008
Preliminary Data Sheet
Ordering and PVR Information
For information on the availability of the following parts, contact your local AMCC sales office. For additional
information on the part number structure see
Figure 1.
Product Name
PPC460GT
PPC460GT
Order Part Number
(see
Notes)
PPC460GT-SpAfff(f)T
PPC460GT-NpAfff(f)T
Package
35mm 728-ball TE-EPBGA
35mm 728-ball TE-EPBGA
Revision
Level
A
A
PVR Value
0x130218A0
0x130218A1
JTAG ID
0x144101E1
0x144101E1
Notes:
Characters following the dash (-):
1.
2.
3.
4.
5.
S = Security feature present, N = Security feature not present
p = Package type: U = lead-free (RoHS compliant), T = contains lead.
A = Chip revision level A
fff(f) = Processor frequency: fff = 600 = 667MHz, fff = 800 = 800MHz, ffff = 1000 = 1GHz
T = Case temperature range of
−40°C
to +85°C.
Each part number contains a revision code. This is the die mask revision number and is included in the part
number for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain
information that uniquely identifies the part. Refer to the
PowerPC 460GT Embedded Processor User’s Manual
for
details on accessing these registers.
Figure 1. Order Part Number Key
PPC460GT-SUA1000T
AMCC Part Number
Security Feature
Package
Case Temperature Range
Processor Frequency
Revision Level
Note:
The example P/N above contains the security feature, is lead-free, is capable of running at 1GHz, and is shipped
in a tray (tape-and-reel packaging is not available).
4
AMCC Proprietary
Revision 1.07 – May 29, 2008
460GT – PPC460GT Embedded Processor
Preliminary Data Sheet
Block Diagram
Figure 2. PPC460GT Functional Block Diagram
16
External
Interrupts
Clock
Control
Reset
Timers
MMU
Power
Mgmt
DCRs
UART IIC(x2)
x4
BSC
DCR Bus
On-chip Peripheral Bus (OPB) - 32 bits, 100 MHz
Arb
SPI
GPIO
GPT
External
Bus
Controller
NAND
Flash
Controller
UIC
PPC440
Processor Core
FPU
JTAG
32KB
I-Cache
Trace
32KB
D-Cache
SRAM
Cntrlr
S2
OCM
64KB
S7
S0
DMA
Cntrlr
(4-Ch)
HSDMA
Cntrlr
S1
OPB
Bridge
S3
Security
Engine
w/Kasumi
S4
TRNG/
PKA
S5
256KB L2 Cache
M0
M1
M3
M4
M6
Low Latency (LL) Segment
M7
M10
M8
M9
Arb
M5
Processor Local Bus (PLB) - 128 bits, 200 MHz
M2
High Bandwidth (HB) Segment
S4
S3
S2
S1
S0
MAL w/
Int. Coalescing
PCI-Express
Int PCI-E0 PCI-E1
Hand (x1)
(x4)
SRIO
PCI
33/66 MHz
32-bit
Memory
Queue
DDR 1 and 2
SDRAM Cntrlr
TAH/QoS
10/100/
10/100/ 1000 x2
1000 x2
Ethernet
1 lane
HSS x1
4 lanes
HSS x1/x4
64+8
SGMII
x3
ZMII
RGMII
Bridge x2 Bridge
Sn = Slave n
Mn = Master n
The PPC460GT is a system on a chip (SOC).
AMCC Proprietary
5
