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PS-702-EDJ-KCBN-742M434700

SAW Oscillator, 742.4347MHz Nom, SMD, 6 PIN

器件类别:无源元件    振荡器   

厂商名称:Microsemi

厂商官网:https://www.microsemi.com

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
Objectid
4005057057
包装说明
SMD, 6 PIN
Reach Compliance Code
compliant
其他特性
TRI-STATE; ENABLE/DISABLE FUNCTION; COMPLIMENTARY OUTPUT
最长下降时间
0.5 ns
频率容差
50 ppm
JESD-609代码
e4
安装特点
SURFACE MOUNT
端子数量
6
标称工作频率
742.4347 MHz
最高工作温度
70 °C
最低工作温度
-20 °C
振荡器类型
SAW OSCILLATOR
输出兼容性
LVDS
封装主体材料
CERAMIC
封装等效代码
DILCC6,.2
物理尺寸
7.49mm x 5.08mm x 2.13mm
最长上升时间
0.5 ns
最大压摆率
70 mA
最大供电电压
3.63 V
最小供电电压
2.97 V
标称供电电压
3.3 V
表面贴装
YES
最大对称度
45/55 %
端子面层
Gold (Au) - with Nickel (Ni) barrier
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PS-702
SAW Based Clock Oscillator
Former Part Number SO-720
PS-702
Description
The PS-702 is a SAW Based Clock Oscillator that achieves low phase noise and very low jitter performance.
The PS-702 is housed in an industry standard 6-Pad leadless ceramic package that is hermetically sealed. Packaging options
include bulk or tape and reel.
Features
Industry Standard Package, 5.0 x 7.5 x 2.0 mm
ASIC Technology For Ultra Low Jitter
0.100 ps-rms typical across 12 kHz to 20 MHz BW
0.120 ps-rms typical across 50 kHz to 80 MHz BW
Output Frequencies from 150 MHz to 1 GHz
3.3 V Operation
LV-PECL or LVDS Con guration with Fast Transition Times
Complementary Outputs
Output Disable Feature
Improved Temperature Stability over Standard SAW XO
Product is free of lead and compliant to EC RoHS Directive
Applications
Reference Clock for Wired and Wireless Products
Description
Standard
1-2-4 Gigabit Fibre Channel
10 Gigabit Fibre Channel
10GbE LAN / WAN
OC-192
SONET / SDH
INCITS 352-2002
INCITS 364-2003
IEEE 802.3ae
ITU-T G.709
GR-253-CORE Issue4
Block Diagram
Vcc
COutput
Output
BAW
SAW
Vc
OD
Page1 of 7
Gnd
Performance Speci cations
Table 1: Electrical Performance
Parameter
Voltage
2, 3
Current (No Load)
3
Nominal Frequency
1, 2
Frequency Stability
1, 2
(Ordering Option)
Aging
6, 8
Outputs
Mid Level - LVPECL
2, 3
Swing - LVPECL
2, 3
Mid Level - LVDS
2, 3
Swing - LVDS
2, 3
Current
6
Rise Time
5, 6
Fall Time
5, 6
Symmetry
2, 3
Jitter
6, 7
(12 kHz - 20 MHz BW) 622.08 MHz
Jitter
6, 7
(50 kHz - 80 MHz BW) 622.08 MHz
Period Jitter
9
, RMS (622.08 MHz)
Period Jitter
9
, Peak - Peak (622.08 MHz)
Operating Temperature
1
Package Size
1]
2]
3]
4]
5]
6]
7]
8]
9]
Symbol
V
CC
I
CC
Min
Supply
2.97
Frequency
Typical
3.3
55
Maximum
3.63
70
1000
Units
V
mA
MHz
ppm
f
N
f
STAB
150
±50, ±100
10
V
CC
-1.4
450
250
I
OUT
t
R
t
F
SYM
фJ
фJ
фJ
фJ
T
OP
45
50
0.100
0.120
2.5
16
0/70, -20/70 or -40/85
5.0 x 7.5 x 2.0
V
CC
-1.25
600
V
CC
-1.2
450
20
500
500
55
0.250
0.300
3.0
24
V
CC
-1.0
750
ppm
V
mV-pp
V
mV-pp
mA
ps
ps
%
ps-rms
ps-rms
ps-rms
ps pk-pk
°C
mm
See Standard Frequencies and Ordering Information tables (Pg 7) for more speci c information
Parameters are tested with production test circuit below (Fig 1).
Parameters are tested at ambient temperature with test limits guard-banded for speci ed operating temperature.
Measured as the maximum deviation from the best straight-line t, per MIL-0-55310.
Measured from 20% to 80% of a full output swing (Fig 2).
Not tested in production, guaranteed by design, veri ed at quali cation.
Integrated across stated bandwidth per GR-253-CORE Issue4.
Tested with Vc = 0.3V to 3.0V unless otherwise stated in part description
Broadband Period Jitter measured using Lecroy Wavemaster 8600A 6 GHz Oscilloscope, 250K samples taken
Enable, Disable
(-1.3V, +2.0V)
1
6
(+2.0V)
t
R
COutput
t
F
No connect
2
5
V
OH
50%
V
OL
(-1.3V)
3
4
50
Output
50
On Time
Test Circuit Notes:
1) To Permit 50
Measurement of Outputs, all DC Inputs are Biased Down 1.3V.
2) All Voltage Sources Contain Bypass Capacitors to Minimize Supply Noise.
3) 50
Terminations are Within Test Equipment.
Period
Fig 1: Test Circuit
Fig 2: LV-PECL Waveform
Page2 of 7
Absolute Maximum Ratings
Parameter
Power Supply
Output Current
Storage Temperature
Soldering Temp/Time
Symbol
V
CC
I
OUT
TS
T
LS
Ratings
0 to 4
25
-55 to 125
260 / 40
Unit
V
mA
°C
°C / sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied
at these or any other conditions in excess of conditions represented in the operational sections of this datasheet. Exposure to
absolute maximum ratings for extended periods may adversely a ect device reliability. Permanent damage is also possible if OD
or Vc is applied before Vcc.
Suggested Output Load Con gurations
+3.3V
0.10
µ
F
0.10
µ
F
+3.3V
+3.3V
0.01
µ
F
0.01
µ
F
150
150
OD
1
2
6
5
Vcc
COutput
Output
Z = 50
Z = 50
100
OD
N/C
1
2
6
Vcc
40
40
N/C
Gnd
5
COutput
Z = 50
3
4
Gnd
3
4
Output
Z = 50
49
49
240
240
LV-PECL to LV-PECL:
For short transmission lengths, the power
consumption could be reduced by removing the 100
resistor and
doubling the value of the pull down resistors.
LV-PECL to LVDS:
Restricted for short transmission lengths.
Configuration may require modification depending on LVDS receiver.
+3.3V
0.10
µ
F
0.10
µ
F
+2.0V
0.01
µ
F
0.01
µ
F
OD
N/C
Gnd
1
2
6
5
Vcc
OD
0.01
µ
F
0.01
µ
F
1
6
Vcc
COutput
N/C
-1.3V
2
3
5
4
COutput
Output
3
4
Output
240
240
Functional Test:
Allows standard power supply configuration.
Since AC coupled, the LV-PECL levels cannot be measured.
Production Test:
Allows direct DC coupling into 50
measurement
equipment. Must bias the power supplys as shown. Similar to Figure 1.
Page3 of 7
Typical Characteristics - Phase Noise
PS-702-ECE-GAAN-622M080000
Page4 of 7
Reliability
VI quali cation includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR re ow
simulation. The PS-702 family is capable of meeting the following quali cation tests:
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitry has been designed into the PS-702 proper precautions should be taken when handling and
mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing and design
protection evaluation.
ESD Ratings
Model
Human Body Model
Man Man Model
Minimum
1500V
200V
Conditions
MIL-STD-883, Method 3015
V/JESD22-A115-A
Re ow Pro le (IPC/JEDEC J-STD-020C)
Parameter
PreHeat Time
Ramp Up
Time Above 217 °C
Time To Peak Temperature
Time at 260 °C
Ramp Down
Symbol
t
S
R
UP
t
L
T
AMB-P
t
P
R
DN
Value
60 sec Min, 180 sec Max
3 °C/sec Max
60 sec Min, 150 sec Max
480 sec Max
20 sec Min, 40 sec Max
6 °C/sec Max
The device is quali ed to meet the JEDEC standard for
Pb-Free assembly. The temperatures and time intervals
listed are based on the Pb-Free small body requirements.
The PS-702 device is hermetically sealed so an aqueous
wash is not an issue.
Termination Plating:
Electroless Gold Plate over Nickel Plate
Page5 of 7
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