C3 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C4 : 0.22~2µF R-category ceramic capacitor for noise filtering.
High-side input (PWM)
(5V line) Note 1,2)
Input signal Input signal Input signal
coditioning coditioning coditioning
Level shifter Level shifter Level shifter
Protection
circuit (UV)
Bootstrap circuit
For detailed description
of the boot-strap circuit
construction, please
contact Mitsubishi
Electric
C4
C3
Protection
circuit (UV)
Protection
circuit (UV)
(Note 6)
DIP-IPM
Inrush current
limiter circuit
Drive circuit Drive circuit Drive circuit
P
AC line input
H-side IGBT
S
(Note 4)
U
V
W
M
AC line output
C
Z
Fig. 3
N
1
V
NC
N
CIN
Drive circuit
L-side IGBT
S
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
Input signal conditioning
Fo logic
Protection
circuit
Control supply
Under-Voltage
protection
F
O
CFO
Low-side input (PWM)
(5V line)
(Note 1, 2) Fault output (5V line)
(Note 3, 5)
Note1:
2:
3:
4:
5:
6:
To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 7)
By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 7)
This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance.
(see also Fig. 7)
The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P and N1 DC power input pins.
Fo output pulse width should be decided by putting external capacitor between CFO and V
NC
terminals. (Example : CFO=22nF
t
FO
=1.8ms (Typ.))
High voltage diodes (600V or more) should be used in the bootstrap circuit.
V
NC
V
D
(15V line)
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Drive circuit
P
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
I
C
(A)
SC Protection
Trip Level
H-side IGBT
S
U
V
W
L-side IGBT
S
External protection circuit
N1
Shunt Resistor
A
N
V
NC
CIN
B
Drive circuit
Collector current
waveform
C R
C
Protection circuit
0
2
t
w
(µs)
Note1:
In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2:
To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Aug. 1999
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21205
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS
(T
j
= 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CC
V
CC(surge)
V
CES
±I
C
±I
CP
P
C
T
j
Parameter
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Condition
Applied between P-N
Applied between P-N
T
C
= 25°C
T
C
= 25°C, instantaneous value (pulse)
T
C
= 25°C, per 1 chip
(Note 1)
Ratings
450
500
600
20
40
56
–20~+150
Unit
V
V
V
A
A
W
°C
Note 1
: The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ T
C
≤
100°C) however, to in-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to T
j(ave)
≤
125°C (@ T
C
≤
100°C).
CONTROL (PROTECTION) PART
Symbol
V
D
V
DB
V
CIN
V
FO
I
FO
V
SC
Parameter
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between V
P1
-V
PC
, V
N1
-V
NC
Applied between V
UFB
-V
UFS
, V
VFB
-V
VFS
,
V
WFB
-V
WFS
Applied between U
P
, V
P
, W
P
-V
PC
, U
N
, V
N
,
W
N
-V
NC
Applied between F
O
-V
NC
Sink current at F
O
terminal
Applied between CIN-V
NC
Ratings
20
20
–0.5~+5.5
–0.5~V
D
+0.5
15
–0.5~V
D
+0.5
Unit
V
V
V
V
mA
V
TOTAL SYSTEM
Parameter
V
CC(PROT)
Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
T
C
T
stg
Storage temperature
V
iso
Isolation voltage
Symbol
Condition
V
D
= V
DB
= 13.5~16.5V, Inverter part
T
j
= 125°C, non-repetitive, less than 2
µs
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
Ratings
400
–20~+100
–40~+125
1500
Unit
V
°C
°C
V
rms
Note 2 : T
C
MEASUREMENT POINT
Control pins
DIP-IPM
Heat sink boundary
Tc
Power pins
Aug. 1999
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21205
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
R
th(j-c)Q
R
th(j-c)F
R
th(c-f)
Parameter
Junction to case thermal
resistance
Contact thermal resistance
Condition
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Case to fin, (per 1 module)
thermal grease applied
Limits
Min.
—
—
—
Typ.
—
—
—
Max.
2.2
4.5
0.067
Unit
°C/W
ELECTRICAL CHARACTERISTICS
(T
j
= 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CE(sat)
V
EC
t
on
t
rr
t
c(on)
t
off
t
c(off)
I
CES
Parameter
Collector-emitter saturation
voltage
FWDi forward voltage
Condition
I
C
= 20A, T
j
= 25°C
V
D
= V
DB
= 15V
V
CIN
= 0V
I
C
= 20A, T
j
= 125°C
T
j
= 25°C, –I
C
= 20A, V
CIN
= 5V
V
CC
= 300V, V
D
= V
DB
= 15V
I
C
= 20A, T
j
= 125°C, V
CIN
= 5V
→
0V
Switching times
Inductive load (upper-lower arm)
Note:
t
on
, t
off
include delay time of the internal control
circuit
T
j
= 25°C
V
CE
= V
CES
T
j
= 125°C
Min.
—
—
—
—
—
—
—
—
—
—
Limits
Typ.
1.8
2.0
2.2
0.8
0.1
0.5
2.0
1.0
—
—
Max.
—
—
—
—
—
—
—
—
1.0
10
Unit
V
V
µs
Collector-emitter cut-off
current
mA
CONTROL (PROTECTION) PART
Symbol
V
D
V
DB
I
D
Parameter
Control supply voltage
Control supply voltage
Condition
Applied between V
P1
-V
PC
, V
N1
-V
NC
Applied between V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
V
P1
-V
PC
, V
N1
-V
NC
V
D
= V
DB
= 15V,
V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
input = OFF
V
D
= V
DB
= 15V,
V
P1
-V
PC
, V
N1
-V
NC
input = ON
V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
V
SC
= 0V, F
O
circuit : 10kΩ to 5V pull-up
V
SC
= 1V, F
O
circuit : 10kΩ to 5V pull-up
V
SC
= 1V, I
FO
= 15mA
T
C
≤
100°C, T
j
≤
125°C
Relates to corresponding input signal for blocking arm
shoot-through.
–20°C
≤
T
C
≤
100°C
(Note 2)
T
j
= 25°C, V
D
= 15°C
T
j
≤
125°C
Trip level
Reset level
Trip level
Reset level
Min.
13.5
13.5
—
—
—
—
4.9
—
0.8
—
3.0
0.45
10.0
10.5
10.3
10.8
1.0
0.8
2.5
0.8
2.5
Limits
Typ.
15.0
15.0
4.25
0.50
4.95
0.50
—
1.0
1.2
5.0
—
0.5
—
—
—
—
1.8
1.4
3.0
1.4
3.0
Max.
16.5
16.5
8.50
1.00
9.70
1.00
—
2.0
1.8
—
—
0.55
12.0
12.5
12.5
13.0
—
2.0
4.0
2.0
4.0
Unit
V
V
mA
mA
mA
mA
V
V
V
kHz
µs
V
V
V
V
V
ms
V
V
Circuit current
V
FOH
V
FOL
V
FOsat
f
PWM
t
dead
V
SC(ref)
UV
DBt
UV
DBr
UV
Dt
UV
Dr
t
FO
V
th(on)
V
th(off)
V
th(on)
V
th(off)
Fault output voltage
PWM input frequency
Allowable deadtime
Short circuit trip level
Supply circuit under-voltage
protection
Fault output pulse width (Note 3)
ON threshold voltage
OFF threshold voltage
ON threshold voltage
OFF threshold voltage
C
FO
= 22nF (connected between CFO–V
NC
)
Applied between:
H-side
U
P
, V
P
, W
P
-V
PC
Applied between:
L-side
U
N
, V
N
, W
N
-V
NC
Note 2 :
Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC trip-
level is less than 34.0 A.
3 :
Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width t
FO
depends on the capacitance value of C
FO
according to the following approximate equation : C
FO
= 12.2
!
10
-6
!
t
FO
[F].
Aug. 1999
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
奈梅亨，2021 年 1 月 12 日：半导体基础元器件领域的高产能生产专家 Nexperia 今天首次宣布推出 80 V RET（配 电阻晶体管 ）系列。这些新的 RET 或“数字晶体管”提供了足够的余量，可用于 48 V 汽车板网（如轻度混合动力和 EV 汽车）和其他更高电压的电路，这些电路经常受到较大的尖峰和脉冲影响，以前的 50 V 器件无法处理。 通过在与晶体管相同的 SO...[详细]
测试/测量
