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PS21865-A

AC Motor Controller, 40A, Hybrid, DIP-41

器件类别：其他集成电路（IC）    信号电路   

厂商名称：Mitsubishi(日本三菱)

厂商官网：http://www.mitsubishielectric.com/semiconductors/

器件标准：  

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参数 预览
器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Mitsubishi(日本三菱)
零件包装代码
QMA
包装说明
,
针数
41
Reach Compliance Code
unknown
ECCN代码
EAR99
模拟集成电路 - 其他类型
AC MOTOR CONTROLLER
JESD-30 代码
R-XQMA-X41
JESD-609代码
e2
功能数量
1
端子数量
41
最大输出电流
40 A
封装主体材料
UNSPECIFIED
封装形状
RECTANGULAR
封装形式
MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）
260
认证状态
Not Qualified
最大供电电压 (Vsup)
16.5 V
最小供电电压 (Vsup)
13.5 V
标称供电电压 (Vsup)
15 V
表面贴装
NO
技术
HYBRID
端子面层
Tin/Copper (Sn/Cu)
端子形式
UNSPECIFIED
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
文档预览
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21865/-A
PS21865/-A
TRANSFER-MOLD TYPE
TRANSFER-MOLD TYPE
INSULATED TYPE
INSULATED TYPE
PS21865
INTEGRATED POWER FUNCTIONS
600V/20A low-loss 5
th
generation IGBT inverter bridge for
3 phase DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
•
•
•
•
•
For upper-leg IGBT
S
: Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection.
For lower-leg IGBT
S
: Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). (Fig.3)
Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).
Input interface : 5V line CMOS/TTL compatible. (High Active)
UL Approved : Yellow Card No. E80276
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
Dimensions in mm
TERMINAL CODE
27×2.8(=75.6)
2.8
±0.3
(8.5) (2.4) (14.4) (2.5) (17.6) (2.4)
1 2
27
3 4
28
29
5 6
30
7 8
31
32
9 10 11
12 13
33
34
14 15 16 17 18 19 20 21
35
36
C
(1)
(4.5)
(3.1)
Heat sink side
(2.2)
(3.5) (4.65)
Type name , Lot No.
41
34.9
±0.5
31
±0.5
2-f4.5
±0.2
(2.9)
37
38
39
(4.65) (10)
40
13.4
±0.5
(1.5)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
UP
VP1
VUFB
VUFS
VP
VP1
VVFB
VVFS
WP
VP1
VPC
VWFB
VWFS
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
VN1
VNC
CIN
CFO
FO
UN
VN
WN
P
U
V
W
N
21.4
±0.5
(11)
(10)
22
23
24
25
26
11.5
±0.5
(0.6)
(2)
(3.5)
DUMMY TERMINAL CODE
27.
28.
29.
30.
31.
32.
33.
34.
VPC
UPG
P
VPC
VPG
U
WPG
V
35.
36.
37.
38.
39.
40.
41.
UNG
VNC
VNO
WNG
VNG
W
P
(1.5)
Irregular solder remains
0.5MAX
Irregular solder remains
0.5MAX
8.5
±0.3
10
±0.3
10
±0.3
10
±0.3
67
±0.3
20
±0.3
(0.6)
(2)
3.8
±0.2
79
±0.5
A
B
½
12.8
±0.5
(16.0)
±0.5
1.9
±0.05
1
±0.2
1.6
±0.5
1.7
±0.05
0.8
±0.2
1.6
±0.5
7
±0.5
3.25MAX
1.85MAX
Detail : B
(t=0.7)
Detail : C
Detail : A
(t=0.7)
Heat sink side
½
-A : Long terminal type (16.0mm)
(0~5°)
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
CBW+
CBW–
CBV+
CBV–
CBU–
CBU+
C1 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.
High-side input (PWM)
(5V line) (Note 1,2)
Input signal Input signal Input signal
conditioning conditioning conditioning
Level shifter Level shifter Level shifter
Protection
circuit (UV)
Protection
circuit (UV)
Protection
circuit (UV)
C2
C1
(Note 6)
DIP-IPM
Inrush current
limiter circuit
P
Drive circuit Drive circuit Drive circuit
AC line input
H-side IGBT
S
(Note 4)
U
V
W
M
AC line output
C
Z
Fig. 3
N1
V
NC
N
CIN
L-side IGBT
S
Drive circuit
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
Input signal conditioning
Fo logic
Protection
circuit
Control supply
Under-Voltage
protection
F
O
CFO
Low-side input (PWM)
(5V line)
(Note 1, 2) Fault output (5V line)
(Note 3, 5)
V
NC
V
D
(15V line)
Note1:
2:
3:
4:
5:
6:
Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 8)
This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistance.
(see also Fig. 8)
The wiring between the power DC link capacitor and the PN1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these PN1 DC power input pins.
Fo output pulse width should be decided by putting external capacitor between CFO and V
NC
terminals. (Example : CFO=22nF
→
t
FO
=1.8ms (Typ.))
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Drive circuit
P
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
I
C
(A)
SC Protection
Trip Level
H-side IGBT
S
U
V
W
L-side IGBT
S
External protection circuit
N1
Shunt Resistor
(Note 1)
A
N
V
NC
CIN
B
Drive circuit
Collector current
waveform
C R
C
Protection circuit
(Note 2)
0
2
t
w
(µs)
Note1:
In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2:
To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS
(T
j
= 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CC
V
CC(surge)
V
CES
±I
C
±I
CP
P
C
T
j
Parameter
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Condition
Applied between P-N
Applied between P-N
T
f
= 25°C
T
f
= 25°C, less than 1ms
T
f
= 25°C, per 1 chip
(Note 1)
Ratings
450
500
600
20
40
52.6
–20~+125
Unit
V
V
V
A
A
W
°C
Note 1
: The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ T
f
≤
100°C) however, to en-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to T
j(ave)
≤
125°C (@ T
f
≤
100°C).
CONTROL (PROTECTION) PART
Symbol
V
D
V
DB
V
IN
V
FO
I
FO
V
SC
Parameter
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between V
P1
-V
PC
, V
N1
-V
NC
Applied between V
UFB
-V
UFS
, V
VFB
-V
VFS
,
V
WFB
-V
WFS
Applied between U
P
, V
P
, W
P
-V
PC
, U
N
, V
N
,
W
N
-V
NC
Applied between F
O
-V
NC
Sink current at F
O
terminal
Applied between CIN-V
NC
Ratings
20
20
–0.5~V
D
+0.5
–0.5~V
D
+0.5
1
–0.5~V
D
+0.5
Unit
V
V
V
V
mA
V
TOTAL SYSTEM
Parameter
Self protection supply voltage limit
V
CC(PROT)
(short circuit protection capability)
Module case operation temperature
T
f
T
stg
Storage temperature
V
iso
Isolation voltage
Symbol
Condition
V
D
= 13.5~16.5V, Inverter part
T
j
= 125°C, non-repetitive, less than 2
µs
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
Ratings
400
–20~+100
–40~+125
2500
Unit
V
°C
°C
V
rms
Note 2 : T
f
MEASUREMENT POINT
Al Board Specification :
Dimensions : 100✕100✕10mm, Finishing : 12s, Warp : –50~100µm
Control Terminals
Groove
DIP-IPM
18mm
13.5mm
P
U
V
W
N
AI board
Power Terminals
FWDi Chip
IGBT Chip
Temp. measurement point
(inside the AI board)
Temp. measurement point
(inside the AI board)
Silicon-grease should be applied evenly with a thickness of 100~200µm
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
R
th(j-f)Q
R
th(j-f)F
Parameter
Junction to case thermal
resistance
(Note 3)
Condition
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Min.
—
—
Limits
Typ.
—
—
Max.
1.90
3.00
Unit
°C/W
°C/W
Note 3:
Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
and heat-sink.
ELECTRICAL CHARACTERISTICS
(T
j
= 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CE(sat)
V
EC
t
on
t
rr
t
c(on)
t
off
t
c(off)
I
CES
Parameter
Collector-emitter saturation
voltage
FWDi forward voltage
Condition
I
C
= 20A, T
j
= 25°C
V
D
= V
DB
= 15V
V
IN
= 5V
I
C
= 20A, T
j
= 125°C
T
j
= 25°C, –I
C
= 20A, V
IN
= 0V
V
CC
= 300V, V
D
= V
DB
= 15V
Switching times
I
C
= 20A, T
j
= 125°C, V
IN
= 0
↔
5V
Inductive load (upper-lower arm)
T
j
= 25°C
T
j
= 125°C
Min.
—
—
—
0.70
—
—
—
—
—
—
Limits
Typ.
1.60
1.70
1.50
1.30
0.30
0.40
1.60
0.50
—
—
Max.
2.10
2.20
2.00
1.90
—
0.60
2.20
0.80
1
10
Unit
V
V
µs
µs
µs
µs
µs
mA
Collector-emitter cut-off
current
V
CE
= V
CES
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
Total of V
P1
-V
PC
, V
N1
-V
NC
V
D
= V
DB
= 15V
V
IN
= 5V
V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
V
D
= V
DB
= 15V Total of V
P1
-V
PC
, V
N1
-V
NC
V
IN
= 0V
V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
V
SC
= 0V, F
O
circuit pull-up to 5V with 10kΩ
V
SC
= 1V, I
FO
= 1mA
T
j
= 25°C, V
D
= 15V
(Note 4)
V
IN
= 5V
Trip level
Reset level
T
j
≤
125°C
Trip level
Reset level
C
FO
= 22nF
(Note 5)
Min.
—
—
—
—
4.9
—
0.43
1.0
10.0
10.5
10.3
10.8
1.0
2.1
0.8
Limits
Typ.
—
—
—
—
—
—
0.48
1.5
—
—
—
—
1.8
2.3
1.4
Max.
5.00
0.40
7.00
0.55
—
0.95
0.53
2.0
12.0
12.5
12.5
13.0
—
2.6
2.1
Unit
mA
mA
mA
mA
V
V
V
mA
V
V
V
V
ms
V
V
I
D
Circuit current
V
FOH
Fault output voltage
V
FOL
Short circuit trip level
V
SC(ref)
Input current
I
IN
UV
DBt
Supply circuit under-voltage
UV
DBr
protection
UV
Dt
UV
Dr
Fault output pulse width
t
FO
ON threshold voltage
V
th(on)
Applied between U
P
, V
P
, W
P
-V
PC
, U
N
, V
N
, W
N
-V
NC
OFF threshold voltage
V
th(off)
Note 4 :
Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC trip-
level is less than 34 A.
5 :
Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width t
FO
depends on the capacitance value of C
FO
according to the following approximate equation : C
FO
= 12.2
✕
10
-6
✕
t
FO
[F].
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21865/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Mounting torque
Weight
Heat-sink flatness
Mounting screw : M4
Condition
Recommended 1.18 N·m
(Note 6)
Min.
0.98
—
–50
Limits
Typ.
—
65
—
Max.
1.47
—
100
Unit
N·m
g
µm
Note 6: Measurement point of heat-sink flatness
+ –
Measurement location
3mm
Heat-sink side
–
+
Heat-sink side
RECOMMENDED OPERATION CONDITIONS
Symbol
V
CC
V
D
V
DB
∆V
D
,
∆V
DB
t
dead
f
PWM
Parameter
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
Condition
Applied between P-N
Applied between V
P1
-V
PC
, V
N1
-V
NC
Applied between V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
Min.
0
13.5
13.0
–1
2
—
—
(Note 7)
(Note 8)
300
–5.0
Limits
Typ.
300
15.0
15.0
—
—
5
—
—
—
Max.
400
16.5
18.5
1
—
—
12
—
5.0
Unit
V
V
V
V/µs
µs
kHz
Arms
ns
V
For each input signal, T
f
≤
100°C
T
f
≤
100°C, T
j
≤
125°C
V
CC
= 300V, V
D
= 15V, fc = 10kHz
Allowable r.m.s. current
I
O
P.F = 0.8, sinusoidal
T
j
≤
125°C, T
f
≤
100°C
PWIN
ON
Minimum input pulse width
V
NC
between V
NC
-N (including surge)
V
NC
variation
Note 7 :
The allowable r.m.s. current value depends on the actual application conditions.
8 :
The input pulse width less than PWIN might make no response.
Jul. 2003
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器件捷径:
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