Preliminary
Data Sheet
PS8551AL4
ANALOG OUTPUT TYPE
OPTICAL COUPLED ISOLATION AMPLIFIER
DESCRIPTION
R08DS0123EJ0100
Rev.1.00
Jun 27, 2014
The PS8551AL4 is an optically coupled isolation amplifier that uses an IC with a high-accuracy sigma-delta A/D
converter and a GaAIAs light-emitting diode with high-speed response and high luminance efficiency on the input side,
and an IC with a high-accuracy D/A converter on the output side.
The PS8551AL4 is designed specifically for high common mode transient immunity (CMTI) and high linearity (non-
linearity). The PS8551AL4 is designed for current and voltage sensing.
FEATURES
• Non-linearity (NL200 = 0.35% MAX.)
• High common mode transient immunity (CMTI = 10 kV/
μ
s MIN.)
• High isolation voltage (BV = 5 000 Vr.m.s.)
• Gain tolerance (G = 7.92 to 8.08 (±1%))
Gain: 8 V/V TYP.
• Package: 8-pin DIP lead bending type (Gull-wing) for long creepage distance for
surface mount (L4)
• Embossed tape product: PS8551AL4-E3: 1 000 pcs/reel
• Pb-Free product
• Safety standards
• UL approved: No. E72422
• CSA approved: No. CA 101391 (CA5A, CAN/CSA-C22.2 60065, 60950)
• SEMKO approved (EN60065, EN60950)
• DIN EN60747-5-5 (VDE0884-5) approved (Option)
1
8
PIN CONNECTION
(Top View)
7
+
6
–
5
SHIELD
2
3
4
1. V
DD
1
2. V
IN+
3. V
IN–
4. GND1
5. GND2
6. V
OUT–
7. V
OUT+
8. V
DD
2
+
APPLICATIONS
• AC Servo, inverter
• Solar power conditioner
• Measurement equipment
R08DS0123EJ0100 Rev.1.00
Jun 27, 2014
–
Page 1 of 18
PS8551AL4
PACKAGE DIMENSIONS (UNIT: mm)
Lead Bending Type (Gull-wing) For Long Creepage Distance For Surface Mount (L4)
Chapter Title
9.25
–0.25
+0.5
10.05±0.4
1.01
–0.2
0.2±0.15
+0.4
6.5
–0.1
+0.5
0.5±0.15
2.54
0.62±0.25
PHOTOCOUPLER CONSTRUCTION
Parameter
Air Distance
Outer Creepage Distance
Isolation Distance
Unit (MIN.)
8 mm
8 mm
0.4 mm
R08DS0123EJ0100 Rev.1.00
Jun 27, 2014
3.7±0.35
3.5±0.2
Page 2 of 18
PS8551AL4
MARKING EXAMPLE
Chapter Title
No. 1 pin
Mark
R
8551A
NT131
Company Initial
Type Number
Assembly Lot
N T 1 31
Week Assembled
Year Assembled
(Last 1 Digit)
In-house Code
(T: Pb-Free)
Rank Code
ORDERING INFORMATION
Part Number
PS8551AL4
PS8551AL4-E3
PS8551AL4-V
PS8551AL4-V-E3
Order Number
PS8551AL4-AX
PS8551AL4-E3-AX
PS8551AL4-V-AX
PS8551AL4-V-E3-AX
Solder Plating
Specification
Pb-Free
(Ni/Pd/Au)
Packing Style
Magazine case 50 pcs
Embossed Tape 1 000
pcs/reel
Magazine case 50 pcs
Embossed Tape 1 000
pcs/reel
Safety Standard
Approval
Standard products
(UL, CSA, SEMKO
approved)
UL, CSA, SEMKO,
DIN EN60747-5-2
(VDE0884-5)
Approved
Application Part
1
Number
*
PS8551AL4
*1
For the application of the Safety Standard, following part number should be used.
R08DS0123EJ0100 Rev.1.00
Jun 27, 2014
Page 3 of 18
PS8551AL4
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, unless otherwise specified)
Parameter
Operating Ambient Temperature
Storage Temperature
Supply Voltage
Input Voltage
2 Seconds Transient Input Voltage
Output Voltage
Isolation Voltage
*1
Chapter Title
Symbol
T
A
T
stg
V
DD
1, V
DD
2
V
IN+
, V
IN−
V
IN+
, V
IN−
V
OUT+
, V
OUT−
BV
Ratings
－40
to
＋105
－55
to＋125
0 to 5.5
－2
to V
DD
1＋0.5
－6
to V
DD
1＋0.5
－0.5
to V
DD
2＋0.5
5 000
Unit
°C
°C
V
V
V
V
Vr.m.s.
*1
AC voltage for 1 minute at T
A
= 25°C, RH = 60% between input and output.
Pins 1-4 shorted together, 5-8 shorted together.
RECOMMENDED OPERATING CONDITIONS
Parameter
Operating Ambient Temperature
Supply Voltage
Input Voltage
*1
(Accurate and Linear)
Symbol
T
A
V
DD
1, V
DD
2
V
IN+
, V
IN−
MIN.
−40
4.5
−200
MAX.
105
5.5
200
Unit
°C
V
mV
*1
Using V
IN−
= 0 V (to be connected to GND1) is recommended. Avoid using V
IN−
of 2.5 V or more, because the
internal test mode is activated when the voltage V
IN−
reaches more than 2.5 V.
R08DS0123EJ0100 Rev.1.00
Jun 27, 2014
Page 4 of 18
PS8551AL4
Chapter Title
ELECTRICAL CHARACTERISTICS (DC Characteristics)
(TYP.: T
A
= 25°C, V
IN+
= V
IN−
= 0 V, V
DD
1 = V
DD
2 = 5 V,
MIN., MAX.: refer to RECOMMENDED OPERATING CONDITIONS, unless otherwise specified)
Parameter
Input Offset Voltage
Symbol
V
os
T
A
= 25°C
Conditions
MIN.
−2
−3
Input Offset Voltage Drift
vs. Temperature
Gain
*1
TYP.
−0.25
−0.25
1.6
MAX.
2
3
10
8.08
Unit
mV
⏐dV
os
/dT
A
⏐
G
⏐dG/dT
A
⏐
*2
μ
V/°C
V/V
V/V°C
−200
mV
≤
V
IN+
≤
200 mV,
T
A
= 25°C
7.92
8
0.0006
Gain Drift vs. Temperature
V
OUT
Non-linearity (200 mV)
vs. Temperature
V
OUT
Non-linearity (100 mV)
*2
NL200
⏐dNL200/dT
A
⏐
NL100
⏐V
IN+
⏐MAX.
I
DD
1
I
DD
2
I
IN+
⏐dI
IN+
/dT
A
⏐
V
OL
V
OH
V
OCM
⏐I
OSC
⏐
R
IN
R
OUT
CMRR
IN
−200
mV
≤
V
IN+
≤
200 mV
0.014
0.0001
0.35
%
%/°C
V
OUT
Non-linearity (200 mV) Drift
−100
mV
≤
V
IN+
≤
100 mV
0.011
320
0.2
%
mV
Maximum Input Voltage before V
OUT
Clipping
Input Supply Current
Output Supply Current
Input Bias Current
Input Bias Current Drift
vs. Temperature
Low Level Saturated Output Voltage
High Level Saturated Output Voltage
Output Voltage (V
IN+
= V
IN−
= 0 V)
Output Short-circuit Current
Equivalent Input Resistance
V
OUT
Output Resistance
Input DC Common-Mode Rejection
Ratio
*3
V
IN+
= 400 mV
V
IN+
=
−400
mV
V
IN+
= 0V
−1
13.5
7.8
−0.65
0.3
16
16
1
mA
mA
μ
A
nA/°C
V
V
V
IN+
=
−400
mV
V
IN+
= 400 mV
V
IN+
= V
IN−
= 0 V
2.2
1.29
3.8
2.55
20
450
4
76
2.8
V
mA
kΩ
Ω
dB
*1
The differential output voltage (V
OUT+
−
V
OUT−
) with respect to the differential input voltage (V
IN+
−
V
IN−
), where V
IN+
=
−200
mV to 200 mV and V
IN−
= 0 V) is measured under the circuit shown in
Fig. 2 NL200, G Test Circuit.
Upon
the resulting chart, the gain is defined as the slope of the optimum line obtained by using the method of least
squares.
*2
The differential output voltage (V
OUT+
−
V
OUT−
) with respect to the differential input voltage (V
IN+
−
V
IN−
) is measured
under the circuit shown in
Fig. 2 NL200, G Test Circuit.
Upon the resulting chart, the optimum line is obtained by
using the method of least squares. Non-linearity is defined as the ratio (%) of the optimum line obtained by dividing
[Half of the peak to peak value of the (residual) deviation] by [full-scale differential output voltage].
For example, if the differential output voltage is 3.2 V, and the peak to peak value of the (residual) deviation is 22.4
mV, while the input V
IN+
is
±200
mV, the output non-linearity is obtained as follows:
NL200 = 22.4/(2
×
3 200) = 0.35%
*3
CMRR
IN
is defined as the ratio of the differential signal gain (when the differential signal is applied between the
input pins) to the common-mode signal gain (when both input pins are connected and the signal is applied). This
value is indicated in dB.
R08DS0123EJ0100 Rev.1.00
Jun 27, 2014
Page 5 of 18
FPGA/CPLD
