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PSD4XX

ZPSD4XX

Low Cost Field Programmable Microcontroller Peripherals

NOT FOR NEW DESIGN

FEATURES SUMMARY

Single Supply Voltage:

– 5 V±10% for PSD4XX

– 2.7 to 5.5 V for PSD4XX-V

Figure 1. Packages

Up to 1 Mbit of UV EPROM

Up to 16 Kbit SRAM

Input Latches

Programmable I/O ports

Page Logic

Programmable Security

PLDCC68 (J)

CLDCC68 (L)

TQFP68 (U)

January 2002

This is information on a product still in production but not recommended for new designs.

1/3

PSD4XX Family

PSD4XX/ZPSD4XX

Field-Programmable Microcontroller Peripherals

Table of Contents

Introduction ...........................................................................................................................................................1

Key Features ........................................................................................................................................................2

Notation ................................................................................................................................................................3

Zero-Power Background .......................................................................................................................................3

Integrated Power Management

Operation ........................................................................................................5

Design Flow ..........................................................................................................................................................6

PSD4XX Family ....................................................................................................................................................7

Table 2. PSD4XX Pin Descriptions......................................................................................................................8

The PSD4XX Architecture ..................................................................................................................................10

9.1 The ZPLD Block..........................................................................................................................................10

9.1.1 The PSD4XXA1 ZPLD Block............................................................................................................10

9.1.1.1 The DPLD ..........................................................................................................................12

9.1.1.2 The GPLD ..........................................................................................................................13

9.1.1.3 TPA Macrocell Structure ...................................................................................................13

9.1.1.4 Port B Macrocell Structure .................................................................................................17

9.1.1.5 The ZPLD Power Management..........................................................................................18

9.1.2 The PSD4XXA2 ZPLD Block............................................................................................................22

9.1.2.1 The DPLD ..........................................................................................................................24

9.1.2.2 The GPLD ..........................................................................................................................26

9.1.2.3 Port A Macrocell Structure .................................................................................................26

9.1.2.4 Port B Macrocell Structure .................................................................................................30

9.1.2.5 Port E Macrocell Structure .................................................................................................33

9.1.2.6 The ZPLD Power Management..........................................................................................34

9.2 Bus Interface...............................................................................................................................................37

9.2.1 Bus Interface Configuration ..............................................................................................................37

9.2.2 PSD4XX Interface to a Multiplexed Bus ...........................................................................................38

9.2.3 PSD4XX Interface to Non-Multiplexed Bus ......................................................................................38

9.2.4 Data Byte Enable..............................................................................................................................42

9.2.5 Optional Features .............................................................................................................................43

9.2.6 Bus Interface Examples....................................................................................................................43

9.3 I/O Ports......................................................................................................................................................48

9.3.1 Standard MCU I/O ............................................................................................................................48

9.3.2 PLD I/O ...........................................................................................................................................48

9.3.3 Address Out......................................................................................................................................49

9.3.4 Address In ........................................................................................................................................49

9.3.5 Data Port ..........................................................................................................................................49

9.3.6 Alternate Function In ........................................................................................................................49

9.3.7 Peripheral I/O ...................................................................................................................................50

9.3.8 Open Drain Outputs..........................................................................................................................50

9.3.9 Port Registers...................................................................................................................................51

9.3.10 Port A – Functionality and Structure.................................................................................................54

9.3.11 Port B – Functionality and Structure.................................................................................................54

9.3.12 Port C and Port D – Functionality and Structure ..............................................................................57

9.3.13 Port E – Functionality and Structure.................................................................................................57

9.4 Memory Block .............................................................................................................................................61

9.4.1 EPROM ............................................................................................................................................61

9.4.2 SRAM ...............................................................................................................................................61

PSD4XX Family

PSD4XX/ZPSD4XX

Field-Programmable Microcontroller Peripherals

Table of Contents

(cont.)

10.0

11.0

12.0

13.0

14.0

15.0

16.0

17.0

18.0

19.0

20.0

9.4.3 Memory Select Map..........................................................................................................................61

9.4.4 Memory Select Map for 8031 Application.........................................................................................62

9.4.5 Peripheral I/O ...................................................................................................................................65

9.5 Power Management Unit ............................................................................................................................67

9.5.1 Standby Mode ..................................................................................................................................67

9.5.2 Other Power Saving Options ............................................................................................................70

Page Register .....................................................................................................................................................72

Security Protection..............................................................................................................................................72

System Configuration .........................................................................................................................................73

12.1 Reset Input ..............................................................................................................................................76

12.2 ZPLD and Memory During Reset.............................................................................................................76

12.3 Register Values During and After Reset..................................................................................................76

12.4 ZPLD Macrocell Initialization ...................................................................................................................76

Specifications......................................................................................................................................................77

13.1 Absolute Maximum Ratings .....................................................................................................................77

13.2 Operating Range .....................................................................................................................................77

13.3 Recommended Operating Conditions......................................................................................................77

13.4 AC/DC Parameters ..................................................................................................................................78

13.5 Example of ZPSD4XX Typical Power Calculation at V

= 5.0 V...........................................................80

13.6 DC Characteristics (5 V ± 10% versions) ................................................................................................81

13.7 AC/DC Parameters – ZPLD Timing Parameters .....................................................................................82

13.8 Microcontroller Interface – AC/DC Parameters .......................................................................................84

13.9 DC Characteristics (ZPSD4XXV Versions) (3.0 V ± 10% versions) ........................................................88

13.10 AC/DC Parameters – ZPLD Timing Parameters (3.0 V ± 10% versions)................................................89

13.11 Microcontroller Interface – AC/DC Parameters (3.0 V± 10% versions)...................................................91

Timing Diagrams.................................................................................................................................................95

Pin Capacitance................................................................................................................................................102

AC Testing ........................................................................................................................................................102

Erasure and Programming................................................................................................................................102

PSD4XX Pin Assignments ................................................................................................................................103

Package Information.........................................................................................................................................105

PSD4XX Product Ordering Information ............................................................................................................110

20.1 PSD4XX Family – Selector Guide .........................................................................................................110

20.2 Part Number Construction .....................................................................................................................111

20.3 Ordering Information..............................................................................................................................111

Programmable Peripheral

PSD4XX Family

Field-Programmable Microcontroller Peripherals

1.0

Introduction

The PSD4XX family is a microcontroller peripheral that integrates high-performance and

user-configurable blocks of EPROM, programmable logic, and SRAM into one part.

The PSD4XX products also provide a powerful microcontroller interface that eliminates the

need for external “glue logic”. The no “glue logic” concept provides a user-programmable

interface to a variety of 8- and 16-bit (multiplexed or non-multiplexed) microcontrollers that

is easy to use. The part’s integration, small form factor, low power consumption, and ease

of use make it the ideal part for interfacing to virtually any microcontroller.

The PSD4XX provides two Zero-power PLDs (ZPLD): a Decode PLD (DPLD) and a

General-purpose PLD (GPLD). A configuration bit (Turbo) can be set by the MCU, and will

automatically place the ZPLDs into Standby Mode if no inputs are changing. The ZPLDs are

designed to consume minimum power using Zero-power CMOS technology that uses only

10 µA (typical) standby current. Unused product terms are automatically disabled, also

reducing power, regardless of the Turbo bit setting.

The main function of the DPLD is to perform address decoding for the internal I/O ports,

EPROM, and SRAM. The address decoding can be based on up to 24 bits of address

inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports

separate program and data spaces (for 8031 compatible MCUs).

The General-purpose PLD (GPLD) can be used to implement various logic functions

defined by the user, such as:

•

State machines

•

Loadable counters and shift registers

•

Inter-processor mailbox

•

External control logic (chip selects, output enables, etc.).

The GPLD has access to up to 59 inputs, 118 product terms, 24 macrocells, and 24 I/O

pins.

PSD4XX Family

1.0

Introduction

(cont.)

The PSD4XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be

individually configured to provide many functions, including the following:

•

MCU I/O

•

GPLD I/O

•

Latched address output (for MCUs with multiplexed data bus)

•

Data bus (for MCUs with non-multiplexed data bus).

The PSD4XX can easily interface with virtually any 8- or 16-bit microcontroller with a

multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the

ZPLDs, enabling the user to generate signals for external devices.

The PSD4XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four

equal-sized blocks. Each block can occupy a different address location, allowing for

versatile address mapping. The access time of the EPROM includes the address latching

and DPLD decoding.

The PSD4XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a

battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a

power failure. Therefore, you can place data in the SRAM that you want to keep after the

power is switched off. Power switchover to the battery automatically occurs when V

drops

below V

stby

A four-bit Page Register enables easy access to the I/O section, EPROM, and SRAM for

microcontrollers with limited address space. The Page Register outputs are connected to

both ZPLDs and thus can also be used for external paging schemes.

The Power Management Unit (PMU) of the PSD4XX enables the user to control the

power consumption on selected functional blocks, based on system requirements.

For microcontrollers that do not generate a chip select input for the PSD, the Automatic

Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down

Mode or Sleep Mode, based on the inactivity of ALE (or AS).

Implementing your design has never been easier than with PSDsoft—ST’s software

development suite. Using PSDsoft, you can do the following:

•

Configure your PSD4XX to work with virtually any microcontroller

•

Specify what you want implemented in the programmable logic using a design file

•

Simulate your design

•

Download your design to the part using a programmer.

2.0

Key Features

Single-chip programmable peripheral for microcontroller-based applications

256K to 1 Mbit of UV EPROM with the following features:

•

Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16

•

Divided into four equally-sized mappable blocks for optimized address mapping

•

As fast as 70 ns access time, which includes address decoding

•

Built-in Zero-power technology

16 Kbit SRAM is configurable as 2K x 8 or 1K x 16. The access time can be as

quick as 70 ns, including address decoding. The contents of the SRAM can be

battery-backed by connecting a battery to the Vstby pin. The SRAM also has built-in

Zero-power technology.

40 I/O pins (divided into five 8-bit ports) that can be individually configured for:

•

Standard MCU I/O

•

PLD/macrocell I/O

•

Latched address output

•

High-order address inputs

•

Special function I/O

•

Open-drain output

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