PSMN9R0-30YL
N-channel TrenchMOS logic level FET
Rev. 03 — 5 January 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converters
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 10 V;
see
Figure 1
and
3
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
30
61
46
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
175 °C
drain current
total power
dissipation
gate-drain charge
total gate charge
Symbol Parameter
Dynamic characteristics
Q
GD
Q
G(tot)
V
GS
= 4.5 V; I
D
= 10 A;
V
DS
= 12 V; see
Figure 14
and
15
V
GS
= 4.5 V; I
D
= 10 A;
V
DS
= 12 V; see
Figure 14
V
GS
= 10 V; I
D
= 15 A; T
j
= 25 °C
-
-
2.4
8.7
-
-
nC
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
6.16
8
mΩ
NXP Semiconductors
PSMN9R0-30YL
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
S
S
S
G
D
Pinning information
Symbol
Description
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN9R0-30YL
LFPAK
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1
and
3
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
Max
30
30
20
43
61
223
46
175
175
55
223
16
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 55 A; V
sup
≤
30 V;
drain-source avalanche R
GS
= 50
Ω;
unclamped
energy
PSMN9R0-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 5 January 2010
2 of 14
NXP Semiconductors
PSMN9R0-30YL
N-channel TrenchMOS logic level FET
80
I
D
(A)
60
003aac545
120
P
der
(%)
80
03aa16
40
40
20
0
0
50
100
150
200
Tmb (°C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aac547
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
10
μs
100
μs
10
1
DC
1 ms
10 ms
100 ms
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN9R0-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 5 January 2010
3 of 14
NXP Semiconductors
PSMN9R0-30YL
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance from junction to
mounting base
Conditions
see
Figure 4
Min
-
Typ
1.9
Max
2.7
Unit
K/W
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
0.1
10
-1
0.05
0.02
single shot
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
P
003aac544
δ
=
t
p
T
t
p
T
t
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN9R0-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 5 January 2010
4 of 14
NXP Semiconductors
PSMN9R0-30YL
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 20 A; V
GS
= 0 V; T
j
= 25 °C; t
av
= 100 ns
V
GS(th)
gate-source threshold
voltage
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C; see
Figure 11
and
12
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C; see
Figure 12
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C; see
Figure 12
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 30 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 30 V; V
GS
= 0 V; T
j
= 150 °C
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 4.5 V; I
D
= 15 A; T
j
= 25 °C
V
GS
= 10 V; I
D
= 15 A; T
j
= 150 °C;
see
Figure 13
V
GS
= 10 V; I
D
= 15 A; T
j
= 25 °C
R
G
Q
G(tot)
gate resistance
total gate charge
f = 1 MHz
I
D
= 10 A; V
DS
= 12 V; V
GS
= 10 V;
see
Figure 14
and
15
I
D
= 0 A; V
DS
= 0 V; V
GS
= 4.5 V
I
D
= 10 A; V
DS
= 12 V; V
GS
= 4.5 V;
see
Figure 14
Q
GS
Q
GS(th)
Q
GS(th-pl)
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
V
DS
= 12 V; R
L
= 0.5
Ω;
V
GS
= 4.5 V;
R
G(ext)
= 4.7
Ω
V
DS
= 12 V; see
Figure 14
and
15
V
DS
= 12 V; V
GS
= 0 V; f = 1 MHz; T
j
= 25 °C;
see
Figure 16
I
D
= 10 A; V
DS
= 12 V; V
GS
= 4.5 V;
see
Figure 14
and
15
Dynamic characteristics
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
17.8
7
8.7
3
1.7
1.3
2.4
2.7
1006
227
119
13
28
19
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
ns
ns
ns
ns
Min
30
27
35
1.3
0.65
-
-
-
-
-
-
-
-
-
Typ
-
-
-
1.7
-
-
-
-
-
-
8.77
-
6.16
0.6
Max
-
-
-
2.15
-
2.45
1
100
100
100
11.03
15
8
1.5
Unit
V
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Ω
Static characteristics
PSMN9R0-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 5 January 2010
5 of 14
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