PT6315
VFD Driver/Controller IC
DESCRIPTION
PT6315 is a Vacuum Fluorescent Display (VFD)
Controller driven on a 1/4 to 1/12 duty factor. Sixteen
segment output lines, 4 grid output lines, 8
segment/grid output drive lines, one display memory,
control circuit, key scan circuit are all incorporated into
a single chip to build a highly reliable peripheral device
for a single chip micro computer. Serial data is fed to
PT6315 via a three-line serial interface. It is housed in
a 44-pin LQFP.
FEATURES
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•
•
•
•
•
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CMOS Technology
Low Power Consumption
Key Scanning (16 x 2 matrix)
Multiple Display Modes: (16 segments, 12 digits to
24 segments, 4 digits)
8-Step Dimming Circuitry
LED Ports Provide (4 channels, 20mA max.)
Serial Interface for Clock, Data Input, Data Output,
Strobe Pins
No External Resistors Needed for Driver Outputs
Available in 44-pin LQFP
APPLICATION
•
Microcomputer Peripheral Devices
BLOCK DIAGRAM
Tel: 886-66296288
‧
Fax: 886-29174598
‧
http://www.princeton.com.tw
‧
2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6315
APPLICATION CIRCUIT
Note: The capacitor (0.1µF) connected between the GND and the VDD pins must be located as close as possible to the PT6315 chip.
V2.8
2
September, 2009
PT6315
ORDER INFORMATION
Valid Part Number
PT6315
Package Type
44-pin, LQFP
Top Code
PT6315
PIN CONFIGURATION
V2.8
3
September, 2009
PT6315
PIN DESCRIPTION
Pin Name
LED1 to LED4
OSC
DOUT
DIN
(Schmitt Trigger)
CLK
(Schmitt Trigger)
STB
(Schmitt Trigger)
K1, K2
VSS
VDD
SG1/KS1 to SG16/KS16
VEE
SG17/GR12 to SG24/GR5
GR4 to GR1
I/O
O
I
O
I
I
I
I
-
-
O
-
O
O
Description
LED Output Pin
Oscillator Input Pin
A resistor is connected to this pin to determine the oscillation
frequency.
Data Output Pin (N-Channel, Open-Drain)
This pin outputs serial data at the falling edge of the shift clock
(starting from the lower bit).
Data Input Pin
This pin inputs serial data at the rising edge of the shift clock
(starting from the lower bit).
Clock Input Pin
This pin reads serial data at the rising edge and outputs data at
the falling edge.
Serial Interface Strobe Pin
The data input after the STB has fallen is processed as a
command. When this in is “HIGH”, CLK is ignored.
Key Data Input Pins
The data inputted to these pins is latched at the end of the
display cycle.
Logic Ground Pin
Logic Power Supply
High-Voltage Segment Output Pins
Also acts as the Key Source.
Pull-Down Level
High-Voltage Segment/Grid Output Pins
High-Voltage Grid Output Pins
Pin No.
1 to 4
5
6
7
8
9
10, 11
12, 44
13, 43
14 to 29
30
31 to 38
39 to 42
V2.8
4
September, 2009
PT6315
INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:
OUTPUT PINS: SGn, GRn
INPUT PINS: DIN, CLK, STB
INPUT PINS: K1, K2
OUTPUT PIN: DOUT
OUTPUT PINS: LED1 TO LED4
V2.8
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September, 2009
NXP MCU
