128 K x 32 Static RAM
PUMA68SV4000X - 010/012/015/017
Issue 5.0 August 1999
Description
The PUMA68 range of devices provide a high
density surface mount industry standard memory
solution which may accommodate various memory
technologies including SRAM, EEPROM and
Flash. The devices are designed to offer a defined
upgrade path and may be user configured as 8, 16
or 32 bits wide.
The PUMA68SV4000X is a 128Kx32 SRAM
module housed in a 68 ‘J’ leaded package which
complies with the JEDEC 68 PLCC standard.
Access times of 10, 12, 15 and 17ns are available.
The 3.3V low voltage device is available to
commercial and industrial temperature grade.
256Kx32 and 512Kx32 SRAM PUMA68 devices
are available in the same footprint to offer a defined
upgrade path.
Block Diagram
A0~A16
/OE
/WE
128K x 8
SRAM
/CS1
/CS2
/CS3
/CS4
D0~7
D8~15
D16~23
D24~31
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
Features
• Access times of 10, 12, 15 and 17ns.
• 3.3V + 10%.
• Commercial and Industrial temperature grades
• JEDEC Standard 68 PLCC footprint.
• Industry standard pinout.
• User configurable as 8 / 16 / 32 bits wide.
• Operating Power (10ns-32 Bit) 2.00W (max)
• Low power standby.
(TTL) 864mW (max)
(CMOS) 22mW (max)
• Low power Data Retention Mode (L-Part)
• Completely Static Operation.
Pin Definition
See page 2.
Pin Functions
Description
Address Input
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power
Ground
Signal
A0~A16
D0~D31
/CS1~4
/WE
/OE
NC
V
CC
V
SS
Package Details
Plastic ‘J’ Leaded JEDEC PLCC
Max. Dimensions (mm) - 25.27 x 25.27 x 5.08
11403 West Bernardo Court, Suite 100, San Diego, CA92127.
TEL (858) 674 2233, Fax No. (858) 674 2230 E-mail:
sales@mosaicsemi.com
Pin Definition - PUMA68SV4000X
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal
V
CC
NC
/CS1
/CS2
/CS3
/CS4
NC
NC
D16
D17
D18
D19
V
SS
D20
D21
D22
D23
V
CC
D24
D25
D26
D27
V
SS
D28
D29
D30
D31
A6
A5
A4
A3
A2
A1
A0
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal
V
CC
A13
A12
A11
A10
A9
A8
A7
D0
D1
D2
D3
V
SS
D4
D5
D6
D7
V
CC
D8
D9
D10
D11
V
SS
D12
D13
D14
D15
A14
A15
A16
/WE
/OE
NC
NC
PAGE 2
Issue 5.0 August 1999
Absolute Maximum Ratings
(1)
DC Operating Conditions
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
DC Output Current
Symbol
V
T
P
T
T
STG
I
OUT
Min
-0.3
to
Max
+4.6
4.0
Unit
V
W
O
-55
to
+125
20
C
mA
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability
Recommended Operating Conditions
Parameter
Supply Voltage
Max Terminal Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
(Commercial
)
(Industrial)
Notes : (1) Pulse Width : -3.0V for less than 5ns.
Symbol
V
CC
V
TERM
V
IH
V
IL
T
A
T
AI
(1)
Min
3.0
-0.3
2.2
-0.3
0
-40
Typ
3.3
-
-
-
-
-
Max
3.6
7.0
V
CC
+0.5
0.8
70
85
Unit
V
V
V
V
O
O
C
C
(I Suffix)
DC Electrical Characteristics
(V
CC
=3.3V+10%, T
A
=-40
O
C to 85
O
C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
32 Bit
16 Bit
8 Bit
Symbol Test Condition
I
LI
I
LO
I
CC32
I
CC16
I
CC8
I
SB
I
SB1
V
OL
V
OH
V
IN
=0V to V
CC
V
I/O
=0V to V
CC
CS =V
IL
,I
I/O
=0mA, f=f
MAX
CS =V
IL
,I
I/O
=0mA, f=f
MAX
CS =V
IL
,I
I/O
=0mA, f=f
MAX
/CS =V
IH
,f=f
MAX
,V
IN
=V
IL
or
V
IH
/CS>V
CC
-0.2V, 0.2V
>V
IN
>V
CC
-0.2V,f=0
I
OL
=8.0mA, V
CC
= Min
I
OH
=-4.0mA, V
CC
= Min
(1)
(1)
(1)
(1)
Min
-10
20
-
-
-
-
-
-
2.4
Typ
-
-
-
-
-
-
-
-
-
Max
10
20
560
400
320
240
8
0.4
-
Unit
µ
A
µ
A
mA
mA
mA
mA
mA
V
V
Standby Supply Current
-L Version
Output Voltage Low
Output Voltage High
Notes
TTL
CMOS
(1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
(2) At f=f
MAX
address and data inputs are cycling at max frequency
(3) All currents are specified for 10ns
PAGE 3
Issue 5.0 August 1999
Capacitance
(V
CC
= 3.3V, T
A
= 25
O
C, F=1MHz.)
Parameter
Input Capacitance, (
Address, /OE, /WE)
Output Capacitance,
8 bit mode (worst case)
Note : These Parameters are calculated not measured.
Symbol
C
IN1
C
I/O
Test Condition
V
IN
=0V
V
I/O
=0V
Min
-
-
Typ Max
-
-
34
42
Unit
pF
pF
Test Conditions
•
•
•
•
•
•
Input pulse levels : 0V to 3.0V
Input rise and fall times : 3ns
Input and Output timing reference levels : 1.5V
Output Load : See Load Diagram.
V
CC
= 3.3V+10%
PUMA module tested in 32 bit mode.
Output Load
I/O Pin
166Ω
1.76V
30pF
Operation Truth Table
/CS1 /CS2 /CS3 /CS4
L
H
H
H
L
H
L
L
H
H
H
L
H
L
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
X
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
X
H
H
H
H
L
H
L
L
H
H
H
L
H
L
L
X
H
/OE
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
X
/WE Supply Current
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
I
CC8
I
CC8
I
CC8
I
CC8
I
CC16
I
CC16
I
CC32
I
CC8
I
CC8
I
CC8
I
CC8
I
CC16
I
CC16
I
CC32
I
CC32
/I
CC16
/I
CC8
I
SB
,I
SB1
Mode
Write D0~D7
Write D8~D15
Write D16~D23
Write D24~D31
Write D0~D15
Write D16~D31
Write D0~D31
Read D0~D7
Read D8~D15
Read D16~D23
Read D24~D31
Read D0~D15
Read D16~D31
Read D0~D31
D0~D31 High-Z
D0~D31 Standby
Notes : H=V
IH
: L=V
IL
: X=V
IH
or V
IL
PAGE 4
Issue 5.0 August 1999
Low V
CC
Data Retention Characteristics - L Version only
Parameter
V
CC
for Data Retention
Data Retention Current
Data Retention Time
Operation Recovery Time
Symbol
V
DR
I
CCDR1
t
CDR
t
R
(1)
Test Condition
/CS=V
CC
-0.2V
V
CC
=2.0V,/CS>V
CC
-
0.2V,V
IN
>0V
See Retention Waveform
See Retention Waveform
Min
2.0
-
t
RC
t
RC
Typ
-
-
-
-
Max
-
3.0
-
-
Unit
V
mA
ns
ns
PAGE 5
Issue 5.0 August 1999
